Memory ODT Preconfiguration for Faster Semiconductor Boot-Up
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Solution Overview
Problem
Existing semiconductor systems face challenges in reducing the time required for boot-up operations, which affects user satisfaction.
Innovation Solution
A semiconductor system with a baseboard management controller (BMC) assigns identifiers to memories within the system, enabling on-die termination (ODT) settings to optimize signal training, thereby reducing boot-up time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If training operations are performed sequentially for each memory, then signal transmission stability is improved, but boot-up time increases
Solution Approach 1:
The patent divides the training operation into two independent phases: (1) ID assignment and ODT setting performed by the BMC in parallel for all memories through the management bus, and (2) signal training performed by the controller through the command address bus. This segmentation allows ODT settings to be configured simultaneously across multiple memories without sequential delays, while maintaining signal stability through dedicated training operations.
Solution Approach 2:
The BMC performs ID assignment and ODT setting operations in advance before the controller initiates signal training. By pre-configuring the ODT settings through the management bus during system initialization, the patent eliminates the need for sequential configuration during boot-up, thereby reducing overall boot-up time while ensuring proper signal termination is already in place for stable transmission.
2Manufacturing precision
If ODT settings are performed sequentially across memories, then configuration accuracy is improved, but system initialization time increases
Solution Approach 1:
The patent separates ODT configuration from signal training by assigning different responsibilities to different controllers. The BMC handles ID assignment and ODT setting for all memories simultaneously through the management bus, while the controller performs signal training through the command address bus. This segmentation enables parallel execution of configuration tasks, improving initialization speed without sacrificing accuracy.
Solution Approach 2:
The BMC acts as an intermediary between the controller and memories, handling ID assignment and ODT setting operations. This intermediary role allows the BMC to manage memory configuration independently and in parallel, while the controller focuses on signal training. The separation of duties through the BMC intermediary enables simultaneous configuration of multiple memories without compromising configuration accuracy.
3Measurement precision
If a dedicated management bus is added for ID assignment, then memory identification accuracy is improved, but system complexity increases
Solution Approach 1:
The management bus performs multiple functions: ID assignment to memories, ODT setting configuration, and system management operations. By making the management bus multi-functional, the patent avoids adding separate dedicated buses for each function. The same management bus infrastructure is used for both ID assignment and ODT configuration, reducing system complexity while maintaining identification accuracy through dedicated protocol handling.
Data Source
AI summary
A semiconductor system may include a semiconductor apparatus; a controller configured to control the semiconductor apparatus through a command address bus and a data bus, and a baseboard management controller configured to control the semiconductor apparatus through a management bus. The semiconductor apparatus includes a plurality of memories each configured to store data under the control of the controller, configured to output data stored in the semiconductor apparatus, and configured to perform an on-die termination (ODT) setting operation based on an identifier (ID) that is assigned by the baseboard management controller.