Independent On-Die Termination Control for Memory Signal Timing
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Solution Overview
Problem
Existing signal transmitting and receiving apparatuses and memory devices face performance degradation due to the simultaneous enabling and disabling of on-die termination circuits, which causes preamble and postamble time issues, especially in mobile electronic devices requiring low power consumption and high-speed operations.
Innovation Solution
The implementation of independently controlled on-die termination circuits for each pin, allowing for differential enable and disable timing to prevent performance degradation by enabling the first on-die termination circuit before the second, thus allowing signal transmission or reception with termination resistance without waiting for the second circuit to be enabled.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die termination circuits are simultaneously enabled and disabled, then signal integrity is maintained through impedance matching, but preamble and postamble time issues occur causing performance degradation
Solution Approach 1:
The patent divides the termination control into separate circuits for different pins (first on-die termination circuit for data pins, second on-die termination circuit for DQS pins). This segmentation allows independent control of enable/disable timing for each pin type, eliminating the need for simultaneous control and reducing preamble/postamble time issues while maintaining signal integrity through targeted termination.
2Speed
If on-die termination circuits are enabled early to allow signal transmission, then operational speed increases, but power consumption increases due to extended enable periods
Solution Approach 1:
The patent enables the first on-die termination circuit before the second on-die termination circuit in a controlled sequence. This preliminary action allows data pins to be ready for signal transmission before DQS pins are activated, optimizing operational speed while the controlled sequencing prevents extended simultaneous enable periods that would increase power consumption.
3Productivity
If independent control of enable and disable timing is implemented for each on-die termination circuit, then performance degradation is prevented and operational efficiency improves, but device complexity increases
Solution Approach 1:
The patent implements independent control by segmenting the termination circuit into separate first and second on-die termination circuits, each with independent enable/disable control. This segmentation allows optimized timing control for different pin types (data pins vs. DQS pins), improving operational efficiency while the modular structure keeps the added complexity manageable and organized.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of signal transmitting and receiving apparatuses by enabling the first on-die termination circuit when the second is disabled, reducing preamble and postamble times and improving overall operational efficiency in mobile devices.
Implementation Method 1
on-die termination is technology for increasing signal integrity by suppressing signal reflection in an interface between a transmitting device and a receiving device
Data Source
AI summary
A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.