Memory ODT Control for Command Reception During Power-Down

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Solution Overview

Problem

Memory devices face challenges in issuing commands effectively when powered down, particularly due to impedance mismatching in transmission lines, leading to signal distortion and interference, which existing technologies fail to adequately address.

Innovation Solution

The implementation of an ODT pin and ODT circuit within the memory device, which receives a control signal to adjust termination resistance or turn off the ODT circuit, allowing for command issuance, such as a refresh or precharge command, even when the device is powered down, by utilizing an ODT detector and controller to generate signals based on the ODT signal and clock signal levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the memory device is powered down to save energy, then power consumption is reduced, but the ability to issue commands and perform control operations is lost

Engineering Contradiction:

Improvepower consumptionVSAvoidcommand issuance capability

Core Design Contradiction:

Use of energy by moving objectVSEase of operation

Solution Approach 1:

The ODT circuit is activated in advance before the memory device is fully powered down. By pre-configuring the termination resistance through the ODT pin, the device maintains signal reception capability during the power-down transition, enabling commands to be issued even when the main power is reduced or cut off.

Inventive Principle:

Principle #10Preliminary action

2Use of energy by moving object

If the receiver is turned off during power down to reduce power consumption, then energy usage decreases, but signal reception and command decoding become impossible

Engineering Contradiction:

Improvereceiver power consumptionVSAvoidsignal reception reliability

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The memory device is segmented into functional blocks with different power states. The ODT circuit and control logic can remain in a low-power standby state while the main receiver and memory arrays are powered down. This segmentation allows selective activation of only the necessary components for command reception, maintaining reliability while minimizing power consumption.

Inventive Principle:

Principle #1Segmentation

3Device complexity

If termination resistance is not adjusted during power down, then device complexity is reduced, but signal distortion and interference increase

Engineering Contradiction:

Improvetermination control complexityVSAvoidsignal distortion

Core Design Contradiction:

Device complexityVSObject-affected harmful factors

Solution Approach 1:

The termination resistance is made dynamic rather than fixed. The ODT circuit can adjust its termination resistance value based on the operational state of the memory device. During power-down modes, the ODT circuit dynamically adjusts the termination resistance to match the impedance of the transmission line, thereby minimizing signal reflections and distortion without requiring complex external circuitry.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8988101B2Method for operating memory device and apparatuses performing the method

Publication Date: 2015.03.24 SAMSUNG ELECTRONICS CO LTD

AI summary

According to example embodiments, a method for operating a memory device includes receiving an on-die termination (ODT) signal through an ODT pin, and issuing a command or controlling an ODT circuit according to the ODT signal.