Memory ODT Resistance Switching for Accurate Write Leveling

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Solution Overview

Problem

Conventional semiconductor memory devices with dynamic ODT function face challenges in performing accurate write leveling operations due to mismatched terminating resistance circuit resistance during write leveling mode, as the resistance is set for read operations rather than write operations, leading to incorrect skew measurement and adjustment.

Innovation Solution

A semiconductor device with a mode register and ODT control circuit that dynamically adjusts the terminating resistance circuit's resistance mode based on the dynamic ODT function's usage state during write leveling mode, allowing for accurate resistance matching to that during write operations, even without a write command.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the dynamic ODT function is active during write leveling mode, then the terminating resistance circuit resistance changes to match read operation conditions, but this causes inaccurate skew measurement because the resistance does not match write operation conditions

Engineering Contradiction:
Improvedynamic ODT functionVSAvoidskew measurement accuracy
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent applies dynamics by making the ODT control circuit dynamically switch between different resistance modes based on the operation type. The control circuit determines whether to use first resistance mode (for read operations) or second resistance mode (for write operations) and transitions between these modes accordingly, enabling the system to adapt to different operational contexts while maintaining measurement accuracy.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the resistance parameter of the terminating resistance circuit based on the operation mode. By setting different resistance values (first resistance for read operations, second resistance for write operations) and switching between these parameter states, the system ensures that the resistance matches the expected operational conditions during write leveling, thereby improving skew measurement accuracy.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If the terminating resistance circuit uses fixed resistance setting during write leveling, then the measurement process is simple, but the skew measurement becomes inaccurate when dynamic ODT function is active

Engineering Contradiction:
Improvewrite leveling operationVSAvoidskew measurement accuracy
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent introduces dynamic behavior to the previously static resistance setting. The ODT control circuit now actively determines and switches resistance modes based on the operation type, transforming the fixed resistance system into a dynamic one that automatically adapts to whether the device is performing read or write operations, thereby maintaining measurement accuracy without complicating the overall process.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements feedback by having the ODT control circuit continuously monitor the operation mode and adjust the resistance setting accordingly. The control circuit receives feedback about whether the device is in read or write mode and responds by switching between first and second resistance modes, ensuring the resistance setting always matches the current operational context for accurate skew measurement.

Inventive Principle:
Principle #23Feedback

3Device complexity

If the resistance of terminating resistance circuit is set for read operation during write leveling, then the circuit configuration is simplified, but write operation performance deteriorates due to mismatched resistance

Engineering Contradiction:
Improveterminating resistance circuit configurationVSAvoidwrite operation correctness
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies dynamics by enabling the resistance setting to change based on the operation type. Instead of using a fixed read-mode resistance configuration, the system dynamically switches to the appropriate resistance mode (first mode for read, second mode for write) ensuring that the resistance setting always matches the current operation, thereby maintaining write operation correctness without permanently increasing device complexity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the resistance parameter dynamically based on operation mode. The terminating resistance circuit transitions between different resistance values (first resistance for read operations, second resistance for write operations) ensuring that the parameter setting always matches the operational requirements, thereby maintaining reliability without requiring separate fixed configurations for each mode.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20100208534A1Semiconductor memory device, memory module including the same, and data processing system
Publication Date: 2010.08.19 LONGITUDE LICENSING LTD
  • US20100208534A1 patent drawing
  • US20100208534A1 patent drawing
  • US20100208534A1 patent drawing

AI summary

To provide a semiconductor device including a skew detecting circuit activated in a write leveling mode, and an ODT control circuit that activates a terminating resistance circuit connected to a data strobe terminal by using an ODT signal. The ODT control circuit selects a first resistance mode when a dynamic ODT is in an unused state in the write leveling mode, and selects a second resistance mode when the dynamic ODT is in a used state in the write leveling mode. With this configuration, a resistance in a used state of the dynamic ODT and that in an unused state of the dynamic ODT can be reproduced in an actual write operation. Consequently, a more accurate write leveling operation can be performed.