Memory Device Offset Calibration for Signal Integrity
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Solution Overview
Problem
High-speed communication between a controller and a memory device, such as DRAM or SRAM, often results in deteriorated signal integrity due to inter-symbol interference (ISI), which affects data transmission quality.
Innovation Solution
A memory device with an on-die termination (ODT) circuit and offset calibration circuit that selectively applies different voltages to receivers to perform offset calibration and feedback, improving signal integrity by compensating for voltage differences and correcting errors in data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed communication is implemented between controller and memory device, then communication speed increases, but signal integrity deteriorates due to inter-symbol interference
Solution Approach 1:
The patent changes voltage parameters by selectively applying different voltages (first voltage and second voltage) to the second input terminals of receivers during offset calibration operations. This voltage parameter adjustment enables the reception interface to compensate for signal degradation and maintain signal integrity at high communication speeds.
Solution Approach 2:
The patent performs offset calibration operations in advance before normal data transmission. By预先 applying different voltages to receivers and calculating offset values beforehand, the system prepares the reception interface to handle high-speed signals with degraded integrity, thereby improving overall communication reliability.
2Reliability
If offset calibration operation is performed to improve signal integrity, then data transmission quality improves, but additional voltage control circuits and operations are required
Solution Approach 1:
The patent makes the first and second switches multi-functional by using them for both voltage selection during offset calibration and normal operation. This universal use of switches reduces the need for dedicated calibration-only circuitry, thereby limiting the increase in device complexity while still achieving improved data transmission quality.
Data Source
AI summary
Disclosed are a memory device that performs offset calibration and a method of operating the memory device. The memory device includes an input/output pad configured to receive data from a device external, an on-die termination (ODT) circuit connected to the input/output pad, a plurality of receivers connected to the ODT circuit and configured to receive the data from the input/output pad, an offset calibration circuit configured to perform an offset calibration operation on data output from the plurality of receivers and output an offset correction, a first switch configured to provide a first voltage to the plurality of receivers, and a second switch configured to provide a second voltage to the plurality of receivers. During the offset calibration operation, the plurality of receivers receive a third voltage in response to the ODT circuit being enabled and the first voltage through the first switch.