Semiconductor Memory Device Offset Voltage Leak Current Control
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Solution Overview
Problem
In cross-point type resistance varying memory devices, the increasing number of non-selected memory cells leads to increased leak current, resulting in higher power consumption and potential operational issues due to reverse bias voltage applied to non-selected memory cells.
Innovation Solution
The semiconductor memory device employs an offset voltage mechanism, where the absolute value difference between voltages applied to non-selected and selected lines is set smaller than that between selected lines, with the offset voltage increasing as the voltage difference between selected lines increases, to reduce leak current and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If reverse bias voltage is applied to non-selected memory cells in cross-point type resistance varying memory, then the memory cell structure can be simplified, but the leak current increases and power consumption increases
Solution Approach 1:
The patent applies different voltage levels to different groups of memory cells based on their selection state. Specifically, it uses multiple voltage levels (first voltage, second voltage, third voltage) applied to different word lines or bit lines to create distinct voltage conditions for selected and non-selected memory cells. This local differentiation allows the structure to remain simple while controlling leak current in non-selected cells by applying appropriate offset voltages.
Solution Approach 2:
The patent changes the voltage parameter applied to non-selected memory cells by introducing offset voltages. Instead of applying uniform reverse bias voltage to all non-selected cells, the system dynamically adjusts the voltage levels based on the operation being performed. This parameter modification reduces the leak current in non-selected cells while maintaining the simplified cross-point structure.
2Quantity of substance
If the number of non-selected memory cells increases, then the memory capacity increases, but the leak current increases
Solution Approach 1:
The patent introduces multiple voltage levels and offset voltages to differentiate between selected and non-selected memory cells. By applying specific voltage combinations (first voltage to selected line, second voltage to non-selected lines with offset), the system can address a large number of memory cells while controlling the leak current in non-selected cells through parameter optimization.
Solution Approach 2:
The patent implements voltage control mechanisms that respond to the operation state of the memory device. The offset voltages applied to non-selected lines are determined based on the current operation (read, write, erase) and the state of selected cells. This feedback-based voltage adjustment ensures that leak current is minimized in non-selected cells while maintaining proper operation of selected cells, even as memory capacity scales up.
Data Source
AI summary
A memory cell array includes memory cells disposed at intersections of first lines and second lines, and each having a rectifying element and a variable resistance element connected in series. A control circuit, when performing an operation to change retained data, applies a first voltage to a selected first line and applies a second voltage to a selected second line; furthermore, applies a third voltage to a non-selected first line; and, moreover, applies a fourth voltage larger than the third voltage to a non-selected second line. An absolute value of a difference between the third voltage and the fourth voltage is set smaller than an absolute value of a difference between the first voltage and the second voltage by an amount of an offset voltage. A value of the offset voltage increases as the absolute value of the difference between the first and second voltages increases.