Stairless 3D Memory Word Lines Using Integrated Line-and-Via Structures
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming stairless structures for vertical NAND strings, particularly in creating integrated line-and-via structures that effectively contact electrically conductive layers and extend through insulating and dielectric material layers without compromising the integrity of the memory array.
Innovation Solution
A method involving the formation of an alternating stack of insulating and sacrificial material layers, followed by the creation of memory openings, filling these openings with memory elements and semiconductor channels, and then forming integrated line-and-via structures by etching and depositing conductive materials to connect electrically conductive layers through dielectric material layers, ensuring vertical extension and lateral spacing for optimal memory device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional stairless structures are formed using conventional methods, then the manufacturing process becomes complex and time-consuming, but the structural integrity and electrical connectivity are maintained
Solution Approach 1:
The patent applies preliminary action by forming sacrificial material layers at specific positions within the alternating stack before forming the memory openings. These sacrificial layers serve as placeholders that guide subsequent processing steps, enabling the formation of integrated line-and-via structures without requiring complex post-processing adjustments. The sacrificial layers are strategically positioned to define the locations where conductive via structures will eventually be formed, streamlining the overall manufacturing process.
Solution Approach 2:
The patent uses sacrificial material layers as intermediary structures that facilitate the formation of the final stairless configuration. These intermediary layers are formed between the insulating and dielectric material layers, and they enable subsequent isotropic etching processes to create the desired three-dimensional structures. After serving their guiding function, the sacrificial layers are removed, leaving behind the intended structural pattern without requiring direct formation of the complex final geometry.
2Reliability
If integrated line-and-via structures are formed to contact electrically conductive layers, then electrical connectivity is improved, but the manufacturing process requires additional etching and deposition steps
Solution Approach 1:
The patent merges the formation of contact holes and via structures into a single integrated process sequence. By combining the isotropic etching of sacrificial layers with the subsequent conductive material deposition, the method creates integrated line-and-via structures that simultaneously establish both electrical contacts and interconnect pathways. This merging of operations reduces the total number of discrete manufacturing steps while ensuring reliable electrical connectivity between the electrically conductive layers and external contacts.
Solution Approach 2:
The patent transitions from two-dimensional planar processing to three-dimensional structure formation by utilizing isotropic etching that extends vertically and laterally simultaneously. The sacrificial material layers are removed through isotropic etching that creates three-dimensional cavities, which are then filled with conductive materials to form via structures that extend in multiple dimensions. This dimensional transition enables the formation of complex interconnect structures that provide reliable electrical connectivity while maintaining manufacturing efficiency.
3Manufacturing precision
If sacrificial material layers are used to form the stairless structure, then the structural precision is improved, but additional materials and processing steps are required
Solution Approach 1:
The patent applies the discarding principle by using sacrificial material layers that are intentionally formed and then completely removed after serving their structural guidance function. These sacrificial layers are deposited in specific patterns within the alternating stack, provide precise structural definition during processing, and are subsequently removed through isotropic etching. The removal of these temporary structures leaves behind the desired stairless configuration with high precision, while the discarded sacrificial materials can be recovered or disposed of in a controlled manner.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of efficient stairless three-dimensional memory devices with improved integration and contact capabilities, enhancing the performance and reliability of vertical NAND strings by ensuring proper electrical connectivity and structural integrity.
Implementation Method 1
forming backside recesses by isotropically etching portions of the sacrificial material layers by introducing an isotropic etchant into the backside trenches
Implementation Method 2
forming electrically conductive layers in the backside recesses
Data Source
AI summary
A memory device includes an alternating stack of insulating layers and composite layers, where each of the composite layers contains an electrically conductive layer and a dielectric material plate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a respective vertical stack of memory elements and a vertical semiconductor channel and a plurality of integrated line-and-via structures. Each of the plurality of integrated line-and-via structures includes a conductive plate portion that contacts the electrically conductive layer of a respective one of the composite layers, and a conductive via portion that is adjoined to a top surface of the conductive plate portion and vertically extends through a respective overlying subset of the insulating layers and a subset of the dielectric material plates of the composite layers.