Semiconductor Memory Operation Control Circuit for Transistor Stress Reduction
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Solution Overview
Problem
Semiconductor memory devices face excessive stress on circuits when signals are fixed to a specific level due to power application during periods without input commands, addresses, or data, leading to potential transistor deterioration.
Innovation Solution
Incorporating a control signal generation circuit and a period signal generation circuit that generate a control signal and a periodically transited period signal, respectively, to output in place of buffered signals from an external device during self-refresh operations when voltage or temperature exceeds set levels, thereby reducing stress on transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signals are fixed to a specific level during self-refresh operation when voltage or temperature exceeds set levels, then the semiconductor memory device can operate in self-refresh mode, but excessive stress is applied to transistors leading to potential deterioration
Solution Approach 1:
The patent applies periodic action by generating a period signal that alternates between first and second levels, replacing the fixed-level buffered signal during self-refresh operation when voltage or temperature exceeds set levels. This periodic switching reduces excessive stress on transistors while maintaining necessary signal levels, thereby improving transistor reliability without compromising device operation
Solution Approach 2:
The patent changes the signal parameter from a fixed level to a periodically varying level. The operation control circuit detects when voltage or temperature exceeds set levels and responds by changing the buffered signal from a constant level to a period signal with alternating levels, thus reducing stress on transistors while maintaining functional operation during self-refresh mode
2Reliability
If a period signal is generated to replace buffered signals during high voltage or temperature self-refresh operations, then stress on transistors is reduced, but the device complexity increases due to additional control circuits
Solution Approach 1:
The patent introduces an operation control circuit as an intermediary component that monitors voltage and temperature levels and controls the signal generation accordingly. This intermediary circuit generates the period signal only when necessary (during high voltage/temperature self-refresh operations), reducing stress on transistors while adding minimal complexity through a dedicated control mechanism
Solution Approach 2:
The operation control circuit automatically detects when voltage or temperature exceeds set levels and autonomously generates the appropriate period signal without external intervention. This self-service approach allows the system to adaptively reduce transistor stress during critical conditions while maintaining simple overall device architecture
Data Source
AI summary
A semiconductor memory device may include a control signal generation circuit, a period signal generation circuit and a selection circuit. The control signal generation circuit may be configured to generate a control signal in response to a mode signal, a voltage detection signal and a temperature detection signal. The period signal generation circuit may be configured to generate a period signal periodically transited in response to the control signal. The selection circuit may be configured to output, in response to the control signal, any one of the period signal and a signal from an external device that is buffered.