Semiconductor Memory Operation Control Circuit for Efficient Access
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Solution Overview
Problem
Conventional pseudo SRAMs face inefficiencies in data transfer rates when performing sequential memory cell accesses due to the need for a dedicated controller and increased system costs associated with implementing page operations.
Innovation Solution
The semiconductor memory system employs an operation control circuit that differentiates between first and second access operations based on the chip enable signal, allowing for concurrent access operations without the need for a dedicated terminal, thereby improving operation efficiency without increasing system costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a dedicated control signal is used to carry out page operation, then the data transfer rate is increased, but a dedicated controller needs to be developed which increases the system cost
Solution Approach 1:
The access terminal is designed to universally accept both normal access commands and page access commands without requiring dedicated control signals or separate terminals. The operation control circuit internally differentiates between the two operation types based on the command structure itself, allowing a single terminal to serve multiple functions and eliminating the need for dedicated controllers
2Reliability
If the chip enable signal is inactivated each time the address is changed, then the memory cell can be accessed, but the data transfer rate decreases when memory cells are sequentially accessed
Solution Approach 1:
The system dynamically adjusts the chip enable signal behavior based on the operation type. For normal access operations, the chip enable signal is inactivated after each address change to ensure proper access. For page access operations, the chip enable signal remains activated throughout the sequence of column address changes, enabling continuous data transfer without repeated signal transitions
Data Source
AI summary
An operation control circuit carries out a first access operation upon receipt of a first access command during activation of a chip enable signal, and carries out a second access operation accessing a memory core in a shorter time than the first access operation, upon receipt of the next access command during activation of the chip enable signal. For this reason, two types of access operations whose access times differ can be carried out by receiving the same access command at the same access terminal. A dedicated terminal for distinguishing between the two types of operations does not need to be formed in a controller, etc., which accesses a semiconductor memory. Selective use of the first and second access operations improves the operation efficiency of the semiconductor memory. Consequently, the operation efficiency of the semiconductor memory can be improved without increasing the cost of a system incorporating the semiconductor memory.