Memory Optimization in Partitioned Systems with Limited MPU Registers

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Solution Overview

Problem

In partitioned systems with multiple memories and a limited number of registers in the memory protection unit (MPU), existing methods for memory optimization often result in local optimality, failing to achieve overall system efficiency and leading to potential data overwriting and access collisions.

Innovation Solution

A computer-implemented method that calculates run-time changes of data based on access statistics and determines optimal data placement in multiple memories, while assigning MPU registers to define memory areas and ensure secure data access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If memory optimization is performed after MPU configuration in partitioned systems, then local optimality is achieved, but overall system efficiency deteriorates and data access collisions occur

Engineering Contradiction:
Improvememory allocation precisionVSAvoidsystem execution efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent performs memory optimization calculations before finalizing the MPU configuration. By calculating run-time changes and determining optimal data placement in advance, the system establishes a memory distribution plan that accounts for multiple tasks and security requirements, preventing data overwriting and access collisions before they occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback mechanism where access statistics are collected and analyzed to calculate run-time changes. This feedback loop allows the system to adjust memory allocation based on actual access patterns, iteratively improving both local and overall optimality while maintaining security constraints.

Inventive Principle:
Principle #23Feedback

2Manufacturing precision

If unlimited registers are available in MPU, then global memory optimality can be achieved, but device complexity and hardware costs increase

Engineering Contradiction:
Improvememory distribution optimalityVSAvoidMPU register quantity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies partial action by using only the necessary number of registers required for the actual memory allocation needs. Instead of allocating unlimited registers, the system calculates the optimal memory distribution first, then assigns only the minimum required registers to describe the boundaries of memory areas, avoiding unnecessary hardware complexity.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the approach from hardware-centric (providing unlimited registers) to software-centric optimization. By using algorithms to calculate optimal placement and dynamically managing the limited registers, the system achieves global optimality through intelligent parameter management rather than brute-force hardware expansion.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If memory areas are strictly separated for security, then data protection is improved, but memory access efficiency deteriorates

Engineering Contradiction:
Improvedata securityVSAvoidmemory access speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments memory into distinct areas with clear boundaries defined by MPU registers, ensuring security isolation between different tasks and applications. Each memory area is carefully delimited to prevent unauthorized access and data overwriting, while the segmentation is optimized to minimize access overhead and maintain efficiency.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12277333B2Computer-implemented method for optimizing the memory of a partitioned system
Publication Date: 2025.04.15 ROBERT BOSCH GMBH
  • US12277333B2 patent drawing
  • US12277333B2 patent drawing
  • US12277333B2 patent drawing

AI summary

A computer-implemented method for optimizing the memory of a partitioned system including multiple memories, at least one processing core, and at least one memory protection unit (MPU), each MPU including multiple registers. The method includes calculating run-time changes of each piece of data of a multitude of data which are to be processed by the processing core, with the respective piece of data being placed in each memory of the multiple memories based on access statistics for the respective piece of data, each piece of data of the multitude of data being assigned to one rights area or multiple rights areas; determining a placement of the data in the memories based on the calculated run-time changes; and allocating the multiple registers of the MPU for the certain placement of the data in the multiple memories, one register of the multiple registers identifying a memory area of the multiple memories.