Memory Ordering Circuits for Spatial Accelerator Consistency
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Solution Overview
Problem
Exascale computing requires high system-level floating point performance within a tight power budget, which classical von Neumann architectures struggle to achieve by simultaneously improving performance and energy efficiency due to out-of-order scheduling, complex register files, and other structural limitations.
Innovation Solution
A spatial array of processing elements, such as a configurable spatial accelerator (CSA), is employed, featuring a heterogeneous array of processing elements connected by lightweight communication networks, executing dataflow graphs directly rather than transforming them into sequential instruction streams, and incorporating memory ordering circuits for efficient memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If classical von Neumann architectures are used to improve system-level floating point performance, then processing speed may increase, but power consumption increases and energy efficiency deteriorates
Solution Approach 1:
The system is divided into multiple processing domains including a host processor and one or more co-processors. Each co-processor contains specialized processing elements organized in arrays, allowing floating point operations to be distributed and executed in parallel. This segmentation enables high performance while maintaining energy efficiency by executing only necessary operations in specialized hardware.
Solution Approach 2:
A domain interface circuit acts as an intermediary between the host processor and co-processors. This interface includes a queue mechanism that buffers and manages data transfer, allowing asynchronous operation and reducing the energy overhead of frequent host-co-processor communications. The intermediary structure enables efficient offloading of floating point operations without requiring continuous host processor involvement.
2Productivity
If out-of-order scheduling and complex register files are implemented to improve performance, then processing capability increases, but device complexity increases
Solution Approach 1:
Complex features such as out-of-order scheduling and complex register files are extracted from the co-processor design and retained only in the host processor. The co-processors use simpler in-order execution with basic register files, significantly reducing their structural complexity while maintaining high productivity through parallel execution and specialized floating point hardware.
Solution Approach 2:
Different parts of the system have different levels of complexity appropriate to their function. The host processor contains the complex control logic and register files needed for general-purpose computing, while co-processors use simplified structures optimized for specific floating point operations. This local differentiation reduces overall system complexity while maintaining high processing capability.
3Use of energy by moving object
If a spatial array of processing elements is used to improve computational density and energy efficiency, then energy consumption per operation decreases, but device complexity increases
Solution Approach 1:
The co-processors are designed to be dynamically configurable through domain interface circuits that can program the processing elements and their interconnections. This dynamic reconfigurability allows the same hardware structure to adapt to different computational tasks, reducing the need for multiple specialized devices and managing the complexity through software control rather than fixed hardware.
Solution Approach 2:
Multiple identical processing elements are arranged in arrays within each co-processor. Each processing element is a replicated instance of a basic computational unit, allowing parallel execution of the same operation on different data. This copying approach achieves high computational density and energy efficiency through parallelism while keeping individual element complexity low.
Data Source
AI summary
Methods and apparatuses relating to consistency in an accelerator are described. In one embodiment, request address file (RAF) circuits are coupled to a spatial array by a first network, a memory is coupled to the RAF circuits by a second network, a RAF circuit is to not issue, into the second network, a request to the memory marked with a program order dependency on a previous request until receiving a first token generated by completion of the previous request to the memory by another RAF circuit, and a second RAF circuit is to not issue, into the second network, a second request to the memory marked with a program order dependency on a first request until receiving a second token sent by a first RAF circuit when a predetermined time period has lapsed since the first request was issued by the first RAF circuit into the second network.