Memory Device With Orthogonal Arrays For In-Memory Computation
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Solution Overview
Problem
In-memory computation processes in pattern recognition and machine learning applications require frequent memory accesses, leading to significant energy consumption and inefficiencies due to the need for external memory interactions.
Innovation Solution
A memory device with two arrays, where data is communicated internally without involving the memory controller, utilizing orthogonal offsetting of memory arrays for efficient data provisioning and computation, enabling power and time-efficient in-memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data is transferred between memory arrays through external memory controller, then device complexity is reduced, but speed and energy efficiency deteriorate
Solution Approach 1:
The patent introduces a vertical dimension for data transfer by implementing direct inter-array communication paths between first and second memory arrays within the same memory device. This bypasses the traditional horizontal external bus path through the memory controller, effectively adding a new dimensional route for data flow that reduces transfer distance and time.
Solution Approach 2:
The patent extracts the data transfer function from the external memory controller and relocates it internally within the memory device. By implementing direct communication interfaces between memory arrays inside the device, the system removes the bottleneck of external controller mediation for specific in-memory computation data transfers.
2Ease of operation
If data is transferred through external memory controller, then ease of operation is maintained, but energy consumption increases
Solution Approach 1:
The memory device performs self-service by enabling internal data transfer between its own memory arrays without requiring external controller intervention. The direct inter-array communication paths allow the memory device to autonomously provision data for in-memory computations, reducing the energy burden on external systems and optimizing power efficiency for frequently accessed data.
3Adaptability or versatility
If external memory interactions are required, then device versatility is maintained, but productivity decreases
Solution Approach 1:
The patent segments memory operations into two categories: general-purpose operations that use the external memory controller for versatility, and specialized in-memory computation operations that use direct internal array communication for high-speed productivity. This segmentation allows the system to optimize for both flexibility and performance depending on the operation type.
Data Source
AI summary
Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.