Memory Device Oscillator Timing Reference Coordination
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Solution Overview
Problem
Existing memory systems face complexity and power inefficiency due to the need for complex circuitry to generate and distribute internal timing references from noisy external clock signals, which is exacerbated by the requirement for phase and frequency locking in memory controllers and devices.
Innovation Solution
Implementing a memory system where each memory device generates its own internal timing reference signal using an integrated oscillator, allowing the memory controller to receive a shared reference signal that simplifies the oscillator design and reduces power consumption by eliminating the need for phase and frequency locking circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a shared external timing reference is used to synchronize operations between controller and memory device, then synchronization is achieved, but the circuitry required to generate and distribute internal timing references becomes complex and power hungry
Solution Approach 1:
The patent extracts the timing reference generation function from the external shared reference and places it within each memory device. Each device generates its own internal timing reference signal independently, removing the need for complex phase and frequency locking circuitry that would otherwise be required to distribute and synchronize a shared external reference across multiple devices.
Solution Approach 2:
The patent segments the timing reference generation function so that each memory device independently generates its own internal timing reference signal rather than relying on a centralized external reference. This segmentation eliminates the need for complex distribution and synchronization circuitry across the system.
2Measurement precision
If phase and frequency locking circuitry is implemented to maintain synchronization with external references, then timing accuracy is improved, but power consumption increases
Solution Approach 1:
Each memory device serves itself by generating its own internal timing reference signal independently without requiring phase or frequency locking to an external reference. This self-service approach eliminates the power-hungry locking circuitry while maintaining adequate timing synchronization for device operations.
3Reliability
If a shared external timing reference is distributed to multiple devices, then system synchronization is achieved, but the distribution network becomes complex and power consuming
Solution Approach 1:
The patent removes the timing reference generation function from the external distribution network and embeds it within each memory device. This extraction eliminates the need for a power-consuming distribution network while maintaining system synchronization through independent local generation of timing signals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in simpler, more power-efficient memory devices and controllers, as the oscillator within the memory device can operate independently of external timing references, reducing overall system complexity and power usage while enabling device-specific bit rates for efficient data communication.
Implementation Method 1
an oscillator in the memory device generates an internal reference signal that is not phase or frequency adjusted with reference to an external timing reference signal
Data Source
AI summary
A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.