Memory Output Buffer Control Circuit for Unstable Data Noise Reduction

Solution Overview

Problem

Nonvolatile memory devices occupy a data line unnecessarily with unstable data due to delays in enabling the output buffer, leading to increased power consumption and noise, and inefficient use of hardware resources.

Innovation Solution

A logic circuit generates an internal enabling signal based on internal flags indicating the completion of a read operation, enabling the output buffer only when stable data is available on the internal bus, thereby reducing the time the data line is occupied with unstable data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the output buffer is enabled immediately when external enabling commands are provided, then the data line becomes available faster, but the data line is occupied unnecessarily with unstable data, increasing power consumption and noise

Engineering Contradiction:

Improvedata availability speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSLoss of energy

Solution Approach 1:

The logic circuit performs preliminary evaluation of internal flags (READ_N and END_READ) before enabling the output buffer. This preliminary action ensures that the buffer is only enabled when stable data is guaranteed to be available, preventing unnecessary occupation of the data line with unstable data and reducing power consumption and noise.

Inventive Principle:

Principle #10Preliminary action

2Speed

If the output buffer is enabled immediately when external enabling commands are provided, then the data line becomes available faster, but noise on the data line increases due to unstable data

Engineering Contradiction:

Improvedata availability speedVSAvoidnoise on data line

Core Design Contradiction:

SpeedVSObject-affected harmful factors

Solution Approach 1:

The logic circuit performs preliminary evaluation of internal flags (READ_N and END_READ) before enabling the output buffer. This preliminary action ensures that the buffer is only enabled when stable data is guaranteed to be available, preventing unnecessary occupation of the data line with unstable data and reducing power consumption and noise.

Inventive Principle:

Principle #10Preliminary action

3Speed

If the output buffer is enabled immediately when external enabling commands are provided, then the data line becomes available faster, but hardware resource utilization decreases

Engineering Contradiction:

Improvedata line availabilityVSAvoidhardware resource utilization

Core Design Contradiction:

SpeedVSProductivity

Solution Approach 1:

The logic circuit performs preliminary evaluation of internal flags (READ_N and END_READ) before enabling the output buffer. This preliminary action ensures that the buffer is only enabled when stable data is guaranteed to be available, preventing unnecessary occupation of the data line with unstable data and reducing power consumption and noise.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS7535774B2Circuit for generating an internal enabling signal for an output buffer of a memory

Publication Date: 2009.05.19 MICRON TECHNOLOGY INC

AI summary

A circuit is for generating an internal enabling signal for the output buffer of a memory as a function of external commands for enabling the memory and for outputting data. The circuit may be input with the external command for enabling the memory and with internally generated flags signaling when the memory is being read and when a read operation of data from the memory ends. The circuit may generate a first intermediate signal having a null logic value when the memory is enabled and the read operation of data from the memory ends. The circuit may further generate the internal enabling signal as a logic NOR between the first intermediate signal and a logic OR between the external command enabling the memory and the external command for outputting data.