Semiconductor Memory Output Circuit Pseudo-Pipeline Architecture
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Solution Overview
Problem
Conventional semiconductor memory devices face limitations in operating frequency due to phase inversion between switch control signals and insufficient time margins in pipeline modes, particularly in the CL3 and CL4 pipeline modes, which restrict the operating frequency and efficiency.
Innovation Solution
The output circuit in the semiconductor memory device incorporates multiple data paths with complementary control signals and clock gaps, utilizing CMOS transistors and flip-flops to generate control signals synchronized with an external clock, allowing for higher frequency operation by mitigating phase inversion and optimizing data transfer timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating speed of semiconductor memory devices is increased, then data transfer efficiency is improved, but phase inversion between switch control signals occurs and operating frequency is limited
Solution Approach 1:
The output circuit is divided into multiple independent data paths (first data path with switches 71, 73 and second data path with switches 74, 76), each handling different phases of data transfer. This segmentation allows parallel operation and eliminates phase inversion by distributing control signals across separate paths with complementary timing.
Solution Approach 2:
The patent implements periodic clocked operation using external clock signal CLK and internal clock signals (SRP, SRPB) to systematically alternate between first and second data paths. This periodic switching with complementary control signals ensures that when one path is active, the other is inactive, preventing phase inversion while maintaining continuous data flow.
2Speed
If CL3 pipeline mode is used to reduce latency, then data output speed is improved, but operating margin becomes insufficient
Solution Approach 1:
The patent implements a dynamic pipeline architecture that can adaptively switch between different operational modes (CL3 and CL4) based on timing requirements. The output circuit uses dynamic control signals (FRDTP1, FRDTP2, SRP1, SRP2) that are generated based on external clock edges, allowing the system to optimize between speed and margin by selecting appropriate pipeline depth and timing for each operation.
3Reliability
If multiple data paths with complementary control signals are implemented, then operating frequency is improved, but circuit complexity increases
Solution Approach 1:
The patent designs the first and second data paths to be functionally identical but operationally complementary, with each path capable of handling the complete data transfer function independently. This universal design allows the circuit to achieve higher frequency operation through parallelism while managing complexity by reusing the same circuit topology (switches, latches, buffers) across multiple paths rather than designing specialized circuits for each function.
Data Source
AI summary
An output circuit of a semiconductor memory device includes a first data path, a second data path and a third data path. The first data path transfers a sense output signal, and latches the sense output signal to output the sense output signal to a first node. The second data path transfers the sense output signal, and latches the sense output signal to output the sense output signal to the first node. The third data path latches a signal of the first node, and transfers the signal of the first node to generate output data. Accordingly, the semiconductor memory device including the output circuit can operate at a relatively higher frequency using a pseudo-pipeline structured circuit, which combines a wave pipeline structure with a full pipeline structure.