Memory Output Circuit With Clock Stability Detection at Startup
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Solution Overview
Problem
High-speed semiconductor memory devices face reliability issues due to insufficient operation margin when operating with high-frequency clocks, leading to data transfer errors, which existing output circuits cannot address by ensuring a stable logic high level signal on the EDC pin during initial operations.
Innovation Solution
A semiconductor memory device with a data clock detection circuit that stabilizes the data clock and outputs a logic high level signal through the EDC pin until the clock is stabilized, enabling error detection and strobe modes, and controlling data output as synchronous or asynchronous based on clock stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a semiconductor memory device operates with a high-frequency clock to achieve high-speed data transfer, then data input/output speed is improved, but operation margin becomes insufficient leading to data transfer errors
Solution Approach 1:
The patent applies preliminary action by detecting clock stability before enabling normal data transfer operations. The clock stability detection circuit evaluates whether the clock signal has settled to a stable state before the memory device begins high-speed data operations, preventing errors that would occur if operations started during clock instability. This preliminary check ensures that high-frequency operations only commence when clock stability is guaranteed.
Solution Approach 2:
The patent introduces an intermediary clock stability detection circuit that mediates between the clock signal source and the data transfer operations. This intermediary component monitors clock signal characteristics and controls the enabling of data transfer circuits based on detected stability, acting as a buffer that prevents unstable clock conditions from directly causing data transfer errors while maintaining high-speed operation capability.
2Productivity
If the semiconductor memory device enables data transfer operations immediately after power supply, then operation speed is improved, but errors occur due to unstable clock signal during initial operation
Solution Approach 1:
The patent implements preliminary action by performing clock stability detection before enabling data transfer operations. The detection circuit evaluates clock signal stability immediately after power supply and only allows data operations to proceed once stability is confirmed, preventing initial operation errors while minimizing delay to productivity.
Solution Approach 2:
The patent employs feedback by using the clock stability detection result to control the enabling of data transfer operations. The detection circuit continuously monitors clock signal characteristics and provides feedback control signals that enable or disable data transfer circuits based on whether stability thresholds are met, ensuring reliable operation while maintaining high productivity.
3Device complexity
If existing output circuits operate during initial clock instability, then device complexity is reduced, but they cannot ensure logic high level signal on EDC pin leading to error detection failures
Solution Approach 1:
The patent introduces an intermediary clock stability detection circuit that sits between the clock source and the output circuits. This intermediary monitors clock stability and controls the enabling of output circuits, ensuring they only operate when clock stability is guaranteed. This adds minimal complexity while reliably preventing error detection failures during initial operation.
Solution Approach 2:
The patent applies preliminary action by having the detection circuit evaluate clock stability before enabling output circuits. This preliminary check ensures that EDC pin operations only commence when clock stability is confirmed, preventing error detection failures without requiring complex redesign of the output circuits themselves.
Data Source
AI summary
A semiconductor memory device is capable of outputting a preset logic level through an EDC pin according to an operation mode during an initial operation, and providing a stable operation according to the specification of the semiconductor memory device just after the input of a data clock (WCK). The semiconductor memory device includes an output circuit configured to output a synchronous data in response to a data clock when the data clock is enabled, and output an asynchronous data when the data clock is disabled, and a data clock detection circuit configured to control outputting the asynchronous data by checking whether the data clock is in a stable state or not.