Memory Output Drive Circuit With Pattern-Based Current Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The slow response time of internal voltage generation circuits in semiconductor memory devices leads to insufficient operational currents during voltage level transitions, resulting in increased output power noise due to the reliance on decoupling capacitors for auxiliary currents.
Innovation Solution
A current supply method that dynamically adjusts current sourcing based on the pattern of input data, utilizing both internal and external voltage-generated currents, with a current control circuit managing the supply to minimize noise by using external voltage during high-to-low transitions and internal voltage during constant or low-to-high transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitors are used to supply auxiliary currents during voltage level transitions, then current sufficiency is improved, but output power noise increases
Solution Approach 1:
The patent applies preliminary action by detecting the transition state of input data before the actual voltage level change occurs. The controller proactively switches the current supply circuit to the external voltage source in advance of the transition, ensuring sufficient current is available without relying on decoupling capacitors. This predictive switching eliminates the need for capacitor discharge that causes noise, while maintaining current sufficiency throughout the transition.
2Device complexity
If internal voltage generation circuits are used to supply operational currents, then device complexity is reduced, but response time increases
Solution Approach 1:
The patent implements multi-functionality by designing a current supply system that can operate in multiple modes: normal operation mode using the internal voltage generation circuit, and transition mode using the external voltage source. The same current supply circuit structure serves both functions by switching between two voltage sources based on the operational state. This approach maintains the simplicity of the internal circuit while gaining the fast response capability of external voltage supply during transitions.
3Speed
If decoupling capacitors are relied upon for transient current, then response speed is improved, but current control precision decreases
Solution Approach 1:
The patent applies feedback by implementing a controller that continuously monitors the state of input data and the operational requirements of the output drive circuit. Based on this feedback, the controller dynamically adjusts the current supply mode, switching between internal voltage generation and external voltage source. This closed-loop control ensures precise current management during transitions, maintaining both fast response speed and accurate current control without the uncontrolled discharge characteristics of decoupling capacitors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces output power noise by ensuring adequate current supply without relying solely on decoupling capacitors, thereby minimizing noise fluctuations during data transitions.
Implementation Method 1
a current supply circuit including a PMOS transistor, and a current control circuit generating a control signal for the PMOS transistor
Data Source
AI summary
An apparatus for supplying current to a semiconductor memory device. A current supply circuit supplies current to an input/output (I/O) drive circuit responsive to a pattern of data input to the I/O drive circuit. The current supply circuit configured to supply current generated by an external voltage to the I/O drive circuit responsive to a first pattern of data input to the I/O drive circuit, and to prevent the current generated by the external voltage from being supplied to the I/O drive circuit responsive to a second pattern of data input to the I/O drive circuit.