Semiconductor Memory Output Enable Signal Generator
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Solution Overview
Problem
Conventional output enable signal generators in semiconductor memory devices face issues with power consumption during active power down mode, leading to abnormal operations due to the disabling of DLL and external clock count circuits, resulting in delayed data output.
Innovation Solution
An output enable signal generator that includes a DLL clock count unit, an external clock count unit, a comparison unit, and an output enable signal generation unit, with a delay unit to synchronize and control the clock enable signal, enabling early stop and restart of count operations to maintain desired CAS latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the DLL clock count unit and external clock count unit are disabled during active power down mode to reduce power consumption, then power consumption is reduced, but the data output timing becomes abnormal and CAS latency cannot be maintained
Solution Approach 1:
The patent applies preliminary action by restarting the external clock count unit before the DLL clock count unit during active power down mode. This sequence ensures that when the read command is executed, the external clock count unit is already ready to provide accurate count values, preventing any timing abnormalities in data output while maintaining power savings during the power down state.
2Reliability
If the count units are continuously operated to maintain accurate CAS latency timing, then data output timing accuracy is maintained, but power consumption increases during active power down mode
Solution Approach 1:
The patent implements periodic action by selectively enabling and disabling the count units based on the clock enable signal state. During active power down mode when CKE is inactive, the count units are disabled to save power. When CKE becomes active, the count units are restarted in a specific sequence to ensure accurate CAS latency timing is restored. This periodic enablement maintains timing accuracy only when needed while reducing power consumption during idle periods.
Data Source
AI summary
A semiconductor memory device includes: a first count unit for counting a delayed locked loop (DLL) clock in response to a clock enable signal; a first delay unit for delaying the clock enable signal for a delay time which corresponds to a delay amount of a delay model included in a DLL circuit; a second count unit for counting an external clock in response to the delayed clock enable signal; a comparison unit for comparing an output of the first count unit with an output of the second count unit in order to generate a latency signal; and an output enable signal generation unit for generating an output enable signal by using the latency signal.