Memory Output Enable Timing Using DLL Clock Synchronization
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Solution Overview
Problem
Semiconductor memory devices face challenges in synchronizing external and internal clock signals due to delays, leading to skew and errors in generating output enable signals, particularly during domain crossing, which affects operation speed and power consumption.
Innovation Solution
A semiconductor memory device utilizing a delay locked loop to detect phase differences between external and DLL clock signals, generating a delay control signal to produce an output enable reset signal, which is used to reset and synchronize the output enable signal generator, ensuring sufficient setup/hold time and minimizing circuit area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a read command synchronized with an external clock signal is synchronized to an internal clock signal for domain crossing, then data can be output synchronized with the internal clock signal, but skew is generated between external and internal clock signals due to delay elements
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the optimal delay value in a lookup table before domain crossing occurs. The output enable signal generating circuit retrieves the pre-computed delay value to compensate for skew, rather than calculating it in real-time during the critical timing window.
Solution Approach 2:
The patent introduces an intermediary mechanism (lookup table with pre-stored delay values) that mediates between the external and internal clock domains. This intermediary provides the optimal compensation value without requiring direct real-time measurement or adjustment during the critical synchronization path.
2Reliability
If multiple flip-flops are arranged in cascade to synchronize the reset signal, then setup/hold time can be secured, but circuit area increases and activation time becomes slow
Solution Approach 1:
The patent applies preliminary action by pre-calculating the optimal delay value and storing it in a lookup table before the reset signal needs to be synchronized. This allows the system to use a simple delay element rather than multiple cascade flip-flops, reducing circuit area while maintaining timing requirements.
Solution Approach 2:
The patent changes the approach from using multiple flip-flops (discrete timing stages) to using a continuously adjustable delay element controlled by a lookup table. This parameter change allows precise delay adjustment without the area overhead of multiple flip-flops in cascade.
3Productivity
If the operation frequency of the semiconductor memory device is increased, then productivity improves, but setup/hold time becomes insufficient leading to errors
Solution Approach 1:
The patent applies dynamics by making the delay value adjustable rather than fixed. The lookup table provides different delay values that can be selected based on operating conditions, allowing the system to maintain adequate setup/hold time even at higher operation frequencies where fixed delay circuits would fail.
Solution Approach 2:
The patent changes the delay parameter dynamically through the lookup table mechanism, allowing the system to optimize timing margins at different operation frequencies. This enables higher productivity while maintaining reliability by adjusting the delay parameter rather than being constrained by a fixed delay value.
4Reliability
If a delay locked loop circuit is used to generate the internal clock signal, then skew can be compensated, but the circuit area increases
Solution Approach 1:
The patent extracts only the essential function of the DLL (delay compensation) and implements it through a simplified mechanism using a lookup table and delay element. Rather than implementing the full DLL circuit with its phase detection and feedback control, the patent takes out just the delay adjustment functionality needed for skew compensation.
Solution Approach 2:
The patent uses a lookup table that stores pre-computed delay values, essentially copying the timing correction information without requiring the complex real-time control circuitry of a full DLL. This allows skew compensation with minimal circuit area by using stored lookup data rather than active feedback control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures stable synchronization of clock signals, maintaining operation speed and reducing power consumption even at increased frequencies, by securing setup/hold time and minimizing circuit area for the output enable signal generating circuit.
Implementation Method 1
The delay locked loop circuit detects a phase difference between an external clock signal CLK_EXT and a feedback clock signal CLK_FDBK, generates a delay control signal CTR_DLY corresponding to the detected phase difference, and generates a DLL clock signal CLK_DLL by delaying the external clock signal CLK_EXT for a time corresponding to the delay control signal CTR_DLY
Data Source
AI summary
A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.