Memory Data Output Timing With Phase-Shifted Divided Clocks
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Solution Overview
Problem
High-speed semiconductor systems face challenges in accurately synchronizing semiconductor apparatuses with increasing clock signal frequencies, leading to difficulties in maintaining operation speed.
Innovation Solution
A semiconductor apparatus is designed with a memory controller and data storage that utilize a clock generation circuit to generate divided clocks with different phases, a trigger circuit to sense logic levels during specific clock periods, and a data output driver to generate output data, ensuring synchronization and improving data output speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the clock signal is increased to improve operation speed, then the operation speed of the semiconductor apparatus is improved, but it becomes difficult to accurately synchronize the semiconductor apparatus with the clock signal
Solution Approach 1:
The clock signal is divided into multiple divided clocks with different phases through a clock generation circuit. This segmentation of the single clock signal into multiple phase-shifted signals allows the data storage to operate at high speeds while maintaining accurate synchronization by using multiple reference points throughout the clock cycle.
Solution Approach 2:
The trigger circuit senses data at specific periodic intervals during low-level periods of divided clocks. By using periodic sensing actions synchronized with the divided clock phases, the system maintains accurate timing even at high operating frequencies, resolving the contradiction between speed and synchronization accuracy.
2Productivity
If data sensing is performed during high-level periods of divided clocks, then data output speed can be increased, but sensing periods may overlap causing synchronization errors
Solution Approach 1:
Instead of sensing data during the high-level periods of divided clocks, the trigger circuit is designed to sense data during the low-level periods. This inversion of the sensing timing prevents overlapping of sensing periods while maintaining high data output speed, as the low-level periods provide sufficient time margins between successive sensing operations.
Data Source
AI summary
A semiconductor apparatus includes a memory controller and data storage configured to input and output data in synchronization with a clock signal provided from the memory controller. The data storage includes a memory cell array and a data output apparatus configure to output read data from the memory cell array by sensing a logic level of the read data during a low-level period of a first clock, which is an inverted signal of a divided clock of the clock signal, and a low-level period of a second clock, the second clock having a set to phase delay amount from the divided clock.