Memory Data Output Circuit With Phase-Based Data Swapping
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Solution Overview
Problem
High clock frequencies in GDDR SDRAM data output circuits lead to reduced effective data output margin and increased power consumption, necessitating a solution to enhance performance while minimizing power usage.
Innovation Solution
A data output circuit that generates first and second clocks using a reference clock, serializes input data using phase information to generate intermediate data, and outputs data through a single line, reducing power consumption and improving data output efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is increased to output more data during a unit time, then the data output performance is improved, but the power consumption increases and the effective margin for data output decreases
Solution Approach 1:
The data output circuit is divided into multiple serialization circuits (first serialization circuit and second serialization circuit) that operate at different clock phases. Each circuit handles a portion of the data serialization independently, allowing the system to achieve high data output performance through parallel processing while maintaining lower clock frequencies for each individual circuit, thus reducing power consumption.
2Productivity
If the clock frequency is increased to output more data during a unit time, then the data output performance is improved, but the effective margin for data output decreases
Solution Approach 1:
The invention uses periodic clock signals with different phases (first clock and second clock) to drive the serialization circuits alternately. This periodic action with phase diversity allows data to be serialized and output in a staggered manner, effectively increasing the data output rate while maintaining adequate timing margins for each individual data transfer operation, thus improving both productivity and reliability.
3Adaptability or versatility
If multiple phase adjustment circuits are added to handle varying clock phases, then the adaptability to different clock phases is improved, but the device complexity increases
Solution Approach 1:
A phase information generator circuit is introduced as an intermediary component that automatically generates phase information based on the actual clock phases. This phase information is then used by the serialization circuits to adjust their operation dynamically. This intermediary approach provides adaptability to different clock phases without requiring complex manual phase adjustment circuits, as the system self-configures based on the generated phase information.
Data Source
AI summary
A memory device includes a memory cell array storing input data, a clock generator circuit generating first clocks and second clocks using a reference clock, a phase information generator circuit comparing a phase of the reference clock and a phase of at least one of the first clocks and the second clocks and generating phase information as a comparison result, an intermediate data generator circuit serializing a part of input data provided from the memory cell array based on the first clocks to generate first data, serializing a remaining part of the input data to generate second data, and selectively swapping the first data and the second data using the phase information to generate intermediate data, and an output data generator circuit serializing the intermediate data using the second clocks, to output output data through one output data line.