Memory Data Output Circuit for Low-Power Special Read Patterns
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Solution Overview
Problem
Current semiconductor memory devices, such as SDRAMs, experience increased power consumption and operation duration during special read operations, which are 'indifferent' to the presence of normal data, as they still perform data access operations like word line enable and bit line precharge, even when reading special data patterns.
Innovation Solution
A semiconductor memory device with a data output circuit that outputs stored data patterns during special read operations without accessing the memory cell, thereby blocking access to the memory cell during these operations to reduce power consumption and operation duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory cell is accessed during special read operations to output data patterns, then the data patterns can be read, but power consumption and operation duration increase
Solution Approach 1:
The patent segments the data output function by providing separate storage units (mode register, configuration register) distinct from the main memory cell array. During special read operations, data patterns are read from these dedicated storage units rather than accessing the memory cell array, thereby eliminating unnecessary memory cell access operations and reducing power consumption while maintaining the capability to output required data patterns.
2Reliability
If the memory cell is accessed during special read operations, then data patterns can be output, but the operation duration increases
Solution Approach 1:
The patent segments the data output function by providing separate storage units (mode register, configuration register) distinct from the main memory cell array. During special read operations, data patterns are read from these dedicated storage units rather than accessing the memory cell array, thereby eliminating unnecessary memory cell access operations and reducing power consumption while maintaining the capability to output required data patterns.
3Ease of operation
If data access operations (word line enable, bit line precharge) are performed during special read operations, then the memory cell can be accessed, but power consumption and operation duration increase
Solution Approach 1:
The patent segments the data output function by providing separate storage units (mode register, configuration register) distinct from the main memory cell array. During special read operations, data patterns are read from these dedicated storage units rather than accessing the memory cell array, thereby eliminating unnecessary memory cell access operations and reducing power consumption while maintaining the capability to output required data patterns.
Solution Approach 2:
The patent implements dynamic control through an output control circuit that detects the type of read operation being performed. When a special read operation is detected, the circuit dynamically blocks access to the memory cell array and directs the output to data patterns stored in the mode register or configuration register. This dynamic switching allows the system to adapt its access pattern based on operation type, eliminating unnecessary word line enable and bit line precharge operations during special reads.
Data Source
AI summary
According to example embodiments, a semiconductor memory device includes a memory cell array, a multi-purpose register, a data output circuit, and a mode register. The memory cell array is configured to store data. The multi-purpose register is configured to store a data pattern. The data output circuit is configured to output the stored data during a first output mode and output the stored data pattern during a second output mode. The mode register is configured to set the first or second output mode according to a logic level of a portion of a content of the mode register.