Memory System Output Timing Adjustment Circuit
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Solution Overview
Problem
In memory systems with multiple devices connected to a controller, variations in delay times cause issues such as reduced latch margin and data collisions due to differences in manufacturing processes and wiring loads, which existing methods struggle to address effectively, especially at high data transmission speeds.
Innovation Solution
The implementation of output timing adjustment circuits in memory chips allows for adjustable output clock signals to synchronize data output across memory devices, ensuring that read data from all devices is available at approximately the same time, thereby matching delay times and preventing data collisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory devices are commonly connected to a memory controller to increase memory capacity, then the memory capacity of the system is improved, but the delay time variation among memory devices increases due to manufacturing process differences and wiring load variations
Solution Approach 1:
The patent applies parameter changes by adjusting the output timing of read data from each memory device using output timing adjustment circuits. Each circuit modifies the delay parameter of its respective memory device's data output based on measured delay characteristics, thereby compensating for manufacturing variations and wiring load differences while maintaining synchronized data arrival at the memory controller
2Manufacturing precision
If delay time adjustment is performed by monitoring delay time as needed, then the delay time variation can be addressed, but the adjustment cannot catch up with data transmission when it is at considerably high speed
Solution Approach 1:
The patent implements preliminary action by measuring the delay time of each memory device in advance and pre-setting the output timing adjustment circuits with appropriate compensation values before high-speed data transmission begins. This preliminary calibration ensures that when high-speed transmission occurs, the delay compensation is already in place and does not require real-time adjustment, thus maintaining synchronization at high speeds
3Productivity
If read data from memory devices with different delay times are continuously accessed, then the data throughput is improved, but the latch margin at the memory controller side decreases and data collisions occur
Solution Approach 1:
The patent changes the output timing parameter of each memory device's read data based on its measured delay characteristics. By adjusting the output timing to compensate for delay variations, all memory devices output their read data in a synchronized manner, preventing data collisions and maintaining adequate latch margins at the memory controller even during continuous high-speed access operations
Data Source
AI summary
A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.