Memory Data Output Timing Control Across Low and High Clock Frequencies
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Solution Overview
Problem
Conventional data output control circuits in semiconductor memory devices face challenges in maintaining accurate data output timing at high frequencies, leading to potential failures due to reduced shifting margins and distorted clock signal phases, which can result in read data not being output at the correct time.
Innovation Solution
A data output control circuit that selectively uses a low frequency mode controller and a high frequency mode controller, along with a selector, to adjust the CAS latency and DLL clock synchronization, allowing for stable data output across a broad range of frequencies by determining the operation mode based on the external clock frequency and using either count shifting or delay modes to ensure precise data output timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the external clock frequency is increased to improve productivity, then the data output cycle is reduced, but the shifting margin is reduced and clock signal distortion occurs
Solution Approach 1:
The patent implements dynamic operation mode selection between count shifting mode and delay mode based on the external clock frequency. When the clock frequency exceeds a threshold, the system automatically switches from count shifting to delay mode, thereby dynamically adapting to frequency changes and maintaining reliable data output timing across different operating conditions
Solution Approach 2:
The patent changes the operational parameters of the data output control circuit by selecting different control modes (count shifting vs. delay) based on the external clock frequency parameter. This parameter-based mode selection allows the circuit to optimize its operation for high-frequency conditions, preventing timing errors and signal distortion
2Measurement precision
If the count shifter shifts the clock signal multiple times to achieve CAS latency, then the data output timing is controlled, but the phase and pulse width distortion occurs at high frequencies
Solution Approach 1:
The patent extracts the frequency-dependent control logic from the uniform count shifting operation. By separating the operation into frequency-based modes, the patent removes the problematic multi-stage shifting operations at high frequencies and replaces them with a simpler delay mode, thereby reducing phase and pulse width distortion
Solution Approach 2:
The patent makes the data output control circuit dynamic by automatically selecting between count shifting mode and delay mode based on the external clock frequency. This dynamic adaptation allows the circuit to use the simpler delay mode when operating at high frequencies, reducing operational complexity and avoiding timing distortion
3Productivity
If the DLL clock pulse width is reduced due to high-frequency operation, then the data output cycle is shortened, but the flip flops fail to shift at exact time points
Solution Approach 1:
The patent changes the operational parameter from count shifting to delay mode when the external clock frequency exceeds a threshold. This parameter change allows the circuit to maintain accurate timing control at high frequencies without relying on multiple flip-flop shifting operations that become unreliable when the DLL clock pulse width is reduced
Data Source
AI summary
A data output control circuit controls a data output in a read operation. A data output control method includes a count shifting mode and a delay mode and can be used in low and high frequency operations, so that a data output can be stably controlled in a broad frequency range. The data output control circuit includes: a low frequency mode controller a high frequency mode controller and a selector selecting any one of first and second command signals through CAS latency information to be output as a data output control signal.