Semiconductor Memory Device With Oval Cross-Section Columns
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Solution Overview
Problem
Existing NAND type flash memory devices face challenges in increasing capacity while maintaining low costs and efficient wiring line resistances, particularly due to the arrangement and shape of memory columnar bodies which can lead to voids and increased resistance in select gate lines and word lines.
Innovation Solution
The semiconductor memory device employs a three-dimensionally arranged memory cell array with memory columnar bodies having an oval cross-section in the X-Y directions, where the length in the X direction is shorter than in the Y direction, allowing for a larger gap between adjacent bodies, facilitating easier deposition of conductive materials and reducing void formation, thus lowering wiring line resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory columnar bodies are arranged in a conventional configuration, then device capacity can be increased, but wiring line resistances increase due to void formation and poor material penetration
Solution Approach 1:
The patent applies asymmetry by configuring memory columnar bodies with non-circular cross-sections (rectangular, triangular, or polygonal shapes) instead of conventional circular shapes. This asymmetric geometry creates optimized spacing and arrangement patterns that improve conductive material penetration while reducing void formation, thereby lowering wiring line resistances while maintaining high device capacity
Solution Approach 2:
The patent transitions from two-dimensional planar memory arrangements to three-dimensional vertically stacked memory columnar bodies. This dimensional change allows for increased storage capacity within a smaller footprint while the specific geometric configuration of the columnar bodies ensures proper conductive material deposition and reduces wiring line resistances
2Ease of manufacture
If conventional circular cross-section memory columnar bodies are used, then manufacturing is simpler, but conductive material deposition is difficult and voids form increasing resistance
Solution Approach 1:
The patent employs asymmetric cross-sectional shapes (rectangular, triangular, or polygonal) for memory columnar bodies. These shapes create gaps and angles that facilitate better conductive material deposition from deposition sources, reducing void formation and improving manufacturing precision while remaining compatible with standard semiconductor fabrication processes
3Quantity of substance
If memory columnar bodies are closely packed to increase capacity, then device capacity increases, but wiring line resistances increase due to reduced material penetration
Solution Approach 1:
The patent uses asymmetric cross-sectional geometries (rectangular, triangular, or polygonal shapes) for memory columnar bodies. This asymmetric configuration optimizes the spacing and arrangement between adjacent columnar bodies, creating pathways that facilitate conductive material penetration even when columnar bodies are closely packed, thereby maintaining low wiring line resistances while maximizing device capacity
Data Source
AI summary
A semiconductor memory device according to an embodiment comprises: when three directions intersecting each other are assumed to be first through third directions, and two directions intersecting each other in a plane extending in the first and second directions are assumed to be fourth and fifth directions, a memory cell array including: a conductive layer stacked in the third direction above a semiconductor substrate and having a first region; and a first columnar body penetrating the first region of the conductive layer in the third direction and including a semiconductor film, the first columnar body having a cross-section along the first and second directions in which, at a first position which is a certain position in the third direction, a length in the fourth direction is shorter than a length in the fifth direction.