Non-Volatile Memory Data Retention Testing via Over-Erase
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Solution Overview
Problem
Current methods for testing data retention in non-volatile memory cells with floating gates require two baking steps, increasing testing time and cost, and may fail to detect defective cells due to slow leakage during the baking process.
Innovation Solution
Applying a single high temperature bake after either over-erasing or over-programming the memory cell using voltages greater than normal operational voltages to accelerate leakage detection, allowing for faster and more efficient data retention testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two baking steps are used for testing data retention, then detection reliability is improved, but testing time increases
Solution Approach 1:
The patent applies over-erase or over-program voltages before the baking step to pre-condition the floating gate with extreme charge states. This preliminary action accelerates leakage detection during the single baking step, eliminating the need for a second bake while maintaining detection reliability.
Solution Approach 2:
The patent changes the voltage parameter by applying over-erase voltages (more negative than normal erase) or over-program voltages (more positive than normal program) to the floating gate. This parameter change creates enhanced leakage currents that can be detected during a single baking step, resolving the contradiction between reliability and time.
2Manufacturing precision
If normal erase or program voltages are used, then manufacturing precision is maintained, but leakage detection sensitivity deteriorates
Solution Approach 1:
The patent applies excessive voltages (over-erase or over-program) that exceed normal operational levels. This excessive action creates pronounced leakage effects that are easier to detect, while the brief duration and controlled application prevent permanent damage to the floating gate structure.
Solution Approach 2:
The patent employs periodic voltage application sequences: normal programming/erasing to establish baseline states, followed by over-erase/over-program pulses for acceleration testing, then return to normal states. This periodic action allows detection of leakage without compromising manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces testing time, enhances detectability of defective cells by accelerating leakage, and improves screening efficiency by ensuring only a single baking step is necessary.
Implementation Method 1
Applying a single high temperature bake after either over-erasing or over-programming the memory cell using voltages greater than normal operational voltages to accelerate leakage detection
Implementation Method 2
A second positive voltage is applied to the coupling gate 26. A third positive voltage is applied to the second region 16. Current is applied to the first region 14. The electrons are attracted to the positive voltage at the second region 16. As they near the floating gate 24, they experience a sudden increase in the electric field caused by the voltage applied to the coupling gate 26, causing the charges to be injected onto the floating gate 24. Thus, programming occurs through the mechanism of hot electron injection.
Implementation Method 3
During the erase operation when charges are removed from the floating gate 24, a high positive voltage is applied to the erase gate 28. A negative voltage or ground voltage can be applied to the coupling gate 26 and/or the word line 20. Charges are transferrer from the floating gate 24 to the erase gate 28 by tunneling through the insulating layer between the floating gate 24 and the erase gate 28. In particular, the floating gate 24 may be formed with a sharp tip facing the erase gate 28, thereby facilitating the Fowler-Nordheim tunneling of electrons from the tip on the floating gate 24 and through the insulating layer between the floating gate 24 and the erase gate 28 onto the erase gate 28.
Data Source
Figure 1~2
Figure 3
AI summary
A method of decreasing the test time to determine data retention of a memory cell having a floating gate for the storage of charges thereon to determine if the memory cell has a leakage current from the floating gate. The memory cell is characterized by the leakage current having a rate of leakage which is dependent upon the absolute value of the voltage of the floating gate. The memory cell is further characterized by a first erase voltage and a first programming voltage applied during normal operation, and a first read current detected during normal operation. The method applies a voltage greater than the first erase voltage to over erase the floating gate. The memory cell including the floating gate is subject to a single high temperature bake. The memory cell is then tested for data retention of the floating gate based on the single high temperature bake.