Semiconductor Memory Device Overdrive Control Circuit
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Solution Overview
Problem
Semiconductor memory devices face challenges in achieving high-speed sensing operations while preventing data inversion due to noise generated by overdrive operations, as the overdrive mechanism can cause potential interference between bit lines, reducing the effectiveness of the sensing operation.
Innovation Solution
A semiconductor memory device design that includes a sense amplifier, driver transistors, and an overdrive transistor, with a control circuit that gradually adjusts the gate-source or gate-drain voltage of the overdrive transistor to prevent sudden potential increases, thereby reducing noise and enhancing the driving capability step by step, allowing for high-speed sensing without data inversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the sense amplifier is structured as an overdriven sense amplifier to accelerate sensing operation, then the sensing speed is improved, but noise is superimposed on the other bit line causing data inversion
Solution Approach 1:
The control circuit performs preliminary action by gradually increasing the gate-source voltage of the overdrive transistor before fully activating it. This staged approach prepares the system for the overdrive operation while minimizing sudden potential changes that cause noise coupling to adjacent bit lines, thus preventing data inversion while still achieving speed acceleration.
Solution Approach 2:
The invention applies dynamics by making the gate-source voltage of the overdrive transistor variable rather than fixed. The control circuit dynamically adjusts the voltage level based on operational requirements, transitioning from a gradual increase phase to a stable high-voltage phase. This dynamic control enables the system to balance between achieving high sensing speed and maintaining data accuracy by suppressing noise coupling.
2Reliability
If the driving capability of the overdrive transistor is designed to be low to suppress noise, then data inversion is prevented, but the sensing operation cannot be sufficiently accelerated
Solution Approach 1:
The control circuit implements periodic action by operating the overdrive transistor in distinct phases: first gradually increasing the gate-source voltage to suppress noise coupling, then maintaining a stable high voltage level to achieve fast sensing operation. This periodic control pattern allows the system to alternately prioritize reliability and speed, ultimately achieving both objectives.
Solution Approach 2:
The invention applies parameter changes by varying the gate-source voltage of the overdrive transistor according to operational stages. The control circuit changes the voltage parameter from a gradually increasing value to a stable high value, enabling the overdrive transistor to provide strong driving capability for fast sensing while the controlled transition minimizes noise coupling to adjacent bit lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses noise generation during overdrive operations, enabling high-speed sensing while preventing data inversion, by gradually increasing the potential of one bit line and reducing the other, thus maintaining accurate data retrieval.
Implementation Method 1
the potential of the bit line Bi+1 adjacent to the bit line Bi is raised via a capacity C1 between the bit lines Bi and Bi+1 when the potential of the bit line Bi is raised to the overdrive potential
Data Source
AI summary
A semiconductor memory device includes transistors that supply a higher write potential and a lower write potential to a sense amplifier, respectively, an overdrive transistor that supplies an overdrive potential to the sense amplifier, and a control circuit that changes a gate-source voltage of the overdrive transistor step by step. By raising a potential of one of paired bit lines to the overdrive potential not suddenly but step by step, an influence of a potential increase on the other bit line via a parasitic capacity is lessened and a malfunction caused by data inversion is prevented.