Semiconductor Memory Overlapping Ratios Equalize RC Delays
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Solution Overview
Problem
Current memory devices face challenges in achieving optimal operational characteristics and reliability due to variations in current paths and resistance-capacitance (RC) delays across different regions, leading to uneven performance during write and read operations.
Innovation Solution
The electronic device incorporates a semiconductor memory with a cross-point array structure and a multi-deck configuration, where column and row lines overlap in a specific manner to adjust overlapping ratios based on current path lengths, ensuring equal RC delays across regions by tuning the overlapping ratios of column and row lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If column lines and row lines are arranged in a regular grid pattern, then the device complexity is reduced and manufacturing is easier, but RC delays become unequal across different regions leading to performance variations
Solution Approach 1:
The patent applies local quality by varying the overlapping ratios of column lines with row lines based on their specific positions in the memory array. Memory cells are divided into multiple regions, and each region has a predetermined overlapping ratio selected from a set of different ratios. This ensures that cells in regions with longer current paths have larger overlapping ratios (providing stronger coupling and lower RC delay), while cells in regions with shorter current paths have smaller overlapping ratios, thereby equalizing RC delays across the entire array without requiring a completely complex non-grid layout.
2Manufacturing precision
If all memory cells have the same overlapping ratio, then the manufacturing process is simpler, but RC delay inequalities cause uneven performance across different regions
Solution Approach 1:
The patent applies parameter changes by systematically varying the overlapping ratio parameter across different regions of the memory array. Instead of using a single uniform overlapping ratio, the design incorporates multiple predetermined overlapping ratios (first, second, third, and fourth ratios) that are assigned to different regions based on their current path characteristics. This controlled variation in the overlapping ratio parameter allows the system to compensate for position-dependent RC delays while maintaining manufacturability through a standardized multi-parameter approach.
3Speed
If the overlapping ratio is increased to reduce RC delay, then read/write speed is improved, but current consumption increases and over-current flow occurs in cells with already short current paths
Solution Approach 1:
The patent applies local quality by assigning different overlapping ratios to different regions based on their specific current path lengths. Cells in regions with longer current paths are assigned larger overlapping ratios to reduce their RC delays and improve speed, while cells in regions with already short current paths are assigned smaller overlapping ratios to prevent excessive current consumption and over-current conditions. This localized optimization ensures that each cell operates at an appropriate current level for its position, improving overall speed without causing energy waste or damage from over-current flow.
Data Source
AI summary
A semiconductor memory includes: first column lines extending in a first direction; first row lines extending in a second direction; first memory cells located between the first row lines and the first column lines; second column lines electrically connected to the first column lines; second row lines extending in the second direction; and second memory cells located between the second row lines and the second column lines. The first column lines and the second column lines may overlap with each other in a third direction. In a first region, current paths on the second row lines are shorter than current paths on the second row lines in a second region. An overlapping ratio of a second column line belonging to the first region with a first column line may be smaller than that of a second column line belonging to the second region with another first column line.