Memory Device Overlapping Read Retry and Command Processing

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Solution Overview

Problem

Memory devices experience performance degradation when read failures occur during the processing of multiple read commands, leading to inefficiencies in data retrieval.

Innovation Solution

Implementing a memory device with a cache buffer that allows for overlapping execution of read retry operations and regular read operations, ensuring that data from successful read commands is cached and output to the controller while retrying failed read commands, thereby minimizing performance drops.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a read retry operation is executed sequentially for a failed read command, then the reliability of data reading is improved, but the productivity of processing multiple read commands deteriorates

Engineering Contradiction:
Improveread success rateVSAvoidread command processing throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements overlapping execution where the read retry operation for the first read command and the read operation for the second read command are executed concurrently rather than sequentially. This allows the memory device to maintain continuous useful action by utilizing idle time periods, thereby improving productivity without compromising the reliability of read retry operations

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The patent introduces a temporal dimension to the read operation scheduling by executing operations in an overlapping time schedule. Instead of completing one read operation entirely before starting the next, the system allows time intervals to overlap between read retry and new read operations, effectively adding a time-layered dimension to command processing that increases throughput while maintaining reliability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If read operations are executed sequentially one after another, then the reliability of each read operation is maintained, but the speed of processing multiple read commands deteriorates

Engineering Contradiction:
Improveread operation stabilityVSAvoidread command processing speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies preliminary action by initiating the read operation for the second read command during the time period when the read retry for the first read command is being executed. This overlapping scheduling allows preliminary preparation and execution of subsequent read operations without waiting for previous operations to fully complete, thereby increasing processing speed while maintaining operational stability through proper resource management

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11507323B2Memory device and operating method thereof
Publication Date: 2022.11.22 SK HYNIX INC
  • US11507323B2 patent drawing
  • US11507323B2 patent drawing
  • US11507323B2 patent drawing

AI summary

Embodiments of the present disclosure relate to a memory device and an operating method thereof. According to the embodiments of the present disclosure, when a read failure for a first read command among a plurality of read commands inputted from a memory controller occurs, the memory device may execute in an overlapping manner, a read retry operation for the first read command and a read operation for a second read command among the plurality of read commands.