Memory Device Overwrite Programming with Adaptive ISPP Pulses

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Solution Overview

Problem

Existing memory devices face challenges in minimizing distribution deterioration of program target memory cells during overwrite operations, particularly when reliability is compromised due to sudden power loss or decreased retention characteristics.

Innovation Solution

The memory device employs an Incremental Step Pulse Program (ISPP) method with adjustable voltage levels and verification operations, where the initial program pulse is set to a lower level for overwrite operations, and the increment is adjusted based on the program counting value to optimize the program loop process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a normal program operation is performed on memory cells with compromised reliability, then the program operation may fail or cause further deterioration, but performing an overwrite operation with standard voltage levels can minimize distribution deterioration of program target memory cells

Engineering Contradiction:

Improvereliability of memory cellsVSAvoiddistribution deterioration of program target memory cells

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the voltage level parameter of the initial program pulse based on the type of program operation. For overwrite operations, a lower voltage level (second level) is used compared to normal program operations (first level). This parameter adjustment prevents excessive voltage stress on memory cells during overwrite, minimizing distribution deterioration while ensuring reliable programming of cells with compromised reliability.

Inventive Principle:

Principle #35Parameter changes

2Manufacturing precision

If the voltage level of the initial program pulse is reduced for overwrite operations, then distribution deterioration is minimized, but the program operation may require more loops to complete

Engineering Contradiction:

Improvedistribution deterioration of program target memory cellsVSAvoidtime required for program operation

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The patent implements a dynamic voltage adjustment strategy where the initial program pulse voltage level is adaptively selected based on the operation type. The control unit dynamically chooses between first level (for normal program) and second level (for overwrite), optimizing the balance between minimizing distribution deterioration and ensuring efficient program completion within acceptable time frames.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent employs periodic program loops with verification operations. The program operation repeats the program loop including voltage application and verification until successful completion. This periodic approach allows the system to apply lower voltage levels safely over multiple cycles, achieving both distribution preservation and eventual successful programming.

Inventive Principle:

Principle #19Periodic action

3Productivity

If the voltage level of the initial program pulse is set to a higher level, then the program operation completes faster, but distribution deterioration of program target memory cells increases

Engineering Contradiction:

Improvespeed of program operationVSAvoiddistribution deterioration of program target memory cells

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies different voltage quality levels to different operation contexts. Normal program operations receive higher voltage quality (first level) for speed, while overwrite operations receive lower voltage quality (second level) to protect memory cell distribution. This local quality differentiation optimizes performance for each operation type without compromising overall system reliability.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach minimizes the distribution deterioration of memory cells during overwrite operations, improving reliability and reducing the time required for successful program operations by optimizing voltage levels and verification processes.

Implementation Method 1

The nonvolatile memory device may perform program and erase operations on the cell by changing the threshold voltage of the cell as electrons are moved by a strong electric field applied to a thin oxide film of the cell.

Methodology Applied

Scientific EffectThreshold voltage change through electric field: Electric Field

Data Source

PatentUS12394488B2Memory device permitting overwrite program operation and operation method thereof

Publication Date: 2025.08.19 SK HYNIX INC

AI summary

A memory device comprising: a memory cell array including memory cells coupled between a word line and a plurality of bit lines, and a control unit suitable for performing a program operation of repeating a program loop including a voltage application operation and a verification operation on the memory cells according to an Incremental Step Pulse Program (ISPP) method until the program operation is performed successfully, wherein the control unit repeatedly performs the program loop by setting a voltage level of an initial program pulse to one of first and second levels according to whether the program operation is an overwrite operation or not, wherein the initial program pulse is to be applied to the word line in the voltage application operation included in an initial program loop of the repeated program loops, and wherein the second level is lower than the first level by a first set level.