Memory Chip Package Architecture with Mixed Process Regions
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Solution Overview
Problem
Current semiconductor manufacturing processes for monolithic ICs face challenges in miniaturization, performance, and yield due to the need for uniform optimization of all circuits on a planar surface, leading to decreased performance and increased costs, especially in memory devices like SRAM and DRAM, which require different manufacturing approaches.
Innovation Solution
The implementation of a microelectronic assembly with multiple IC dies, each optimized for specific functionalities, such as SRAM and DRAM, using different process regions with varying transistor sizes and conductive trace pitches, connected through advanced interconnects like silicon interposers and EMIB, allowing for high-density interconnections and efficient power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If monolithic IC fabrication is used to integrate multiple memory types on a single planar surface, then integration is achieved, but manufacturing precision and performance deteriorate due to the inability to optimize each memory type independently
Solution Approach 1:
The patent divides the monolithic IC into multiple process regions, each dedicated to fabricating a specific memory type (e.g., SRAM region, DRAM region). This segmentation allows each region to be optimized independently with specialized transistor sizes, conductive trace pitches, and manufacturing processes, resolving the contradiction between integration and performance optimization.
2Ease of manufacture
If uniform transistor sizes and conductive trace pitches are used across the entire IC, then manufacturing simplicity is maintained, but performance and miniaturization are limited
Solution Approach 1:
The patent implements local quality by assigning different transistor sizes and conductive trace pitches to different process regions based on their specific memory type requirements. For example, SRAM regions use larger transistors with wider trace pitches for stability, while DRAM regions use smaller transistors with tighter trace pitches for high density. This local customization enables both manufacturing feasibility and superior performance.
3Device complexity
If a single fabrication process is used for all memory circuits, then process complexity is reduced, but yield and cost-effectiveness decrease
Solution Approach 1:
The patent segments the fabrication process into multiple specialized processes, each tailored to a specific memory type's requirements. This allows each memory region to be manufactured with optimal process parameters, thereby improving yield and cost-effectiveness despite the increased overall process complexity.
4Stability of the object's composition
If all circuits are optimized uniformly on a planar surface, then design consistency is maintained, but miniaturization and high-density interconnections are hindered
Solution Approach 1:
The patent applies local quality by allowing different process regions to have different design characteristics optimized for their specific functions. This enables high-density interconnections in regions where needed while maintaining appropriate design consistency within each specialized region, thereby achieving miniaturization without sacrificing design integrity.
Data Source
AI summary
Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit; a second IC die; a third IC die; and a package substrate. The second IC die is between the first IC die and the package substrate. The first IC die includes: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.