Memory Package Redistributing Layer for Signal Efficiency
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Solution Overview
Problem
The increasing demand for efficient memory storage in electronic devices requires a more effective way to connect memory chips and buffer chips within memory packages and storage devices, as existing technologies struggle to optimize signal paths and channel management efficiently.
Innovation Solution
The implementation of a memory package with a redistribution layer on the package substrate, allowing for multiple signal paths and chip pads connected via wires, enabling efficient electrical connections between memory chips and a buffer chip, which is also connected to a device controller through a system substrate, facilitating multi-channel operations and increased storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory chips are connected using traditional wire bonding methods, then the connection is simple to implement, but the signal transmission efficiency and storage capacity are limited
Solution Approach 1:
The patent transitions from traditional planar wire bonding to a three-dimensional connection architecture using redistribution layers and multiple signal paths. Memory chips are stacked vertically and connected through multiple layers of redistribution layers, enabling signals to travel through multiple dimensions rather than just horizontal planes, thus improving transmission efficiency while managing complexity through structured layering.
Solution Approach 2:
The connection structure is divided into multiple independent signal paths and channels. Each memory chip group is connected to the buffer chip through dedicated signal paths formed by redistribution layers, allowing parallel signal transmission and improving overall efficiency. The segmentation of signal paths enables independent optimization of each connection route.
2Productivity
If a single buffer chip controls all memory chips, then the device structure is simplified, but the channel management efficiency decreases
Solution Approach 1:
The buffer chip is divided into multiple independent buffer chip groups, with each group managing specific memory chip groups through dedicated channels. This segmentation allows parallel processing of multiple memory operations simultaneously, improving channel management efficiency. Each buffer chip group can independently control its assigned memory chips without interfering with other channels.
Solution Approach 2:
Each buffer chip group is designed with multi-functional capabilities to handle various memory operations (read, write, erase) across multiple memory chip groups. The buffer chips can dynamically allocate and manage channels based on operational requirements, providing universal control functionality that improves efficiency without requiring dedicated buffer chips for each memory chip.
3Quantity of substance
If memory chips are stacked in a single layer, then the package area is minimized, but the storage capacity is limited
Solution Approach 1:
The patent implements vertical stacking of memory chips in multiple layers on the package substrate. Redistribution layers are formed at different heights and depths to establish electrical connections between stacked memory chips and the buffer chip. This three-dimensional arrangement dramatically increases storage capacity within a compact footprint by utilizing the vertical dimension rather than expanding horizontally.
Solution Approach 2:
Multiple memory chips are nested vertically in stacked configurations, with each chip positioned above or below others. The redistribution layers are similarly nested across multiple layers, with lower layers providing foundation connections and upper layers establishing additional pathways. This nested structure maximizes the use of available space while maintaining electrical connectivity throughout the stack.
Data Source
AI summary
A memory package includes a package substrate including a redistribution layer and bonding pads connected to the redistribution layer, the redistribution layer including a plurality of signal paths; a buffer chip mounted on the package substrate and including a plurality of chip pads corresponding to a plurality of memory channels; and a plurality of memory chips stacked on the package substrate and divided into a plurality of groups corresponding to the plurality of memory channels, wherein memory chips of a first group, among the plurality of memory chips, are connected to first chip pads of the plurality of chip pads through first wires, and wherein memory chips of a second group, among the plurality of memory chips, are connected to second chip pads of the plurality of chip pads through second wires and at least a portion of the plurality of signal paths.