Memory Package Scribe-Line Layout for Reusable Photomasks
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Solution Overview
Problem
Conventional memory chip manufacturing processes require multiple photolithographic operations for different sizes, increasing time and cost due to specific layout designs and photomasks needed for each size.
Innovation Solution
A memory device package with a substrate featuring a scribe line region connecting two memory chips, allowing for electrical connection through circuit layers extending across the scribe line, enabling customization of memory capacities without redesigning routing or photomasks, and allowing multiple memory chips to be bundled into a single chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithographic operations with specific layout designs and photomasks are used for different memory chip sizes, then manufacturing precision and adaptability are improved, but manufacturing time and cost increase
Solution Approach 1:
The patent applies universality by designing a single photomask that can be used across multiple memory chip sizes. The photomask includes a common active area that can be selectively defined as different chip sizes through scribe line positioning, eliminating the need for multiple size-specific photomasks and layout designs. This universal approach reduces manufacturing time while maintaining precision through the consistent photomask design.
Solution Approach 2:
The patent segments the manufacturing process by separating the photomask design from the chip size definition. The photomask is divided into a common active area and variable scribe line regions, allowing the same photomask to produce different chip sizes by adjusting where scribe lines are positioned. This segmentation enables one photomask to serve multiple chip size requirements without compromising manufacturing precision.
2Manufacturing precision
If multiple photolithographic operations with specific layout designs and photomasks are used for different memory chip sizes, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent reduces manufacturing cost by making photomasks universal across different chip sizes. Instead of requiring separate photomasks for each chip size, a single photomask design can produce multiple chip sizes by varying scribe line positions. This universality eliminates the need to design, fabricate, and store multiple photomasks, significantly reducing photolithography costs while maintaining layout precision.
Solution Approach 2:
The patent merges multiple chip size productions into a single photomask design. The common active area of the photomask serves all chip sizes simultaneously, combining what would traditionally require separate photomasks into one unified design. This merging reduces the total number of photomasks needed, lowering manufacturing costs while preserving the precision required for different chip dimensions.
3Adaptability or versatility
If memory chips are separated into individual chips, then chip customization is improved, but device complexity increases
Solution Approach 1:
The patent uses segmentation to enable chip customization through controlled separation. The wafer is divided into individual chips by introducing scribe lines at specific positions after the common photolithographic process. This segmentation allows flexible customization of chip sizes and configurations while keeping the separation process simple and standardized, avoiding complex custom fabrication for each chip type.
Solution Approach 2:
The patent applies preliminary action by completing all common photolithographic processing on the entire wafer before separation. The active area, circuit patterns, and other common features are formed in advance while the wafer is still intact, allowing efficient bulk processing. Customization is then achieved through simple subsequent steps of positioning scribe lines and separating individual chips, reducing overall process complexity.
Data Source
AI summary
A memory device package and a method of manufacturing a memory device package. The memory device package includes a substrate having a first chip region, a second chip region, and a first scribe line region connected between the first chip region and the second chip region. The memory device package also includes a first memory chip disposed over the first chip region and a second memory chip disposed over the second chip region.