Memory Package Scribe Line Layout for Reusable Photomasks

Solution Overview

Problem

Conventional memory chip manufacturing processes require multiple photolithographic operations for different sizes, increasing time and cost due to specific layout designs and photomasks needed for each size.

Innovation Solution

A memory device package design with a substrate featuring a scribe line region that allows for bundling memory chips of different capacities, using circuit layers extending across the scribe line to electrically connect chips, reducing the need for redesigning routing and photomasks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple photolithographic processing operations are performed for memory chips of different sizes, then memory chips of various capacities can be manufactured, but time and cost of manufacturing increase significantly

Engineering Contradiction:

Improvememory chip capacity customizationVSAvoidmanufacturing time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent implements a universal substrate design with standardized chip regions and scribe line regions that can accommodate multiple memory chip capacities (e.g., 2Gb, 4Gb, 8Gb) using the same photomasks. The substrate includes first and second chip regions with memory chips of different capacities, connected through scribe line regions with circuit layers, allowing a single photomask set to produce multiple product variants without redesign.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple photolithographic processing operations with specific layouts and photomasks are performed for different memory chip sizes, then customized memory capacities are achieved, but manufacturing cost increases

Engineering Contradiction:

Improvememory chip capacity customizationVSAvoidmanufacturing cost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent implements a universal substrate design with standardized chip regions and scribe line regions that can accommodate multiple memory chip capacities (e.g., 2Gb, 4Gb, 8Gb) using the same photomasks. The substrate includes first and second chip regions with memory chips of different capacities, connected through scribe line regions with circuit layers, allowing a single photomask set to produce multiple product variants without redesign.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If memory chips of different sizes are manufactured with multiple photolithographic operations, then various memory capacities are produced, but device complexity increases

Engineering Contradiction:

Improvememory chip capacity varietyVSAvoidrouting design complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The substrate is segmented into distinct functional regions: first chip regions for first memory chips, second chip regions for second memory chips, and scribe line regions containing circuit layers. This segmentation allows independent design and fabrication of memory chip regions while using standardized scribe line regions for interconnection, simplifying the overall routing design process.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements a universal substrate design with standardized chip regions and scribe line regions that can accommodate multiple memory chip capacities (e.g., 2Gb, 4Gb, 8Gb) using the same photomasks. The substrate includes first and second chip regions with memory chips of different capacities, connected through scribe line regions with circuit layers, allowing a single photomask set to produce multiple product variants without redesign.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250309133A1Memory device package having scribe line and method for manufacturing the same

Publication Date: 2025.10.02 NAN YA TECH

AI summary

A memory device package and a method of manufacturing a memory device package. The memory device package includes a substrate having a first chip region, a second chip region, and a first scribe line region connected between the first chip region and the second chip region. The memory device package also includes a first memory chip disposed over the first chip region and a second memory chip disposed over the second chip region.