Multi-Chip Memory Package Layout for Speed and Yield
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Solution Overview
Problem
The increasing integration of semiconductor devices to achieve high operating speed and low power consumption leads to a reduction in electrical properties and production yield, necessitating improvements in semiconductor packages.
Innovation Solution
A semiconductor package comprising two semiconductor chips, one with a controller and a single-level-cell memory cell array, and the other with a multi-level-cell memory cell array, connected through driver circuits to enhance electrical properties and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the integration of semiconductor devices is increased to achieve high operating speed and low power consumption, then operating speed and power consumption are improved, but electrical properties and production yield deteriorate
Solution Approach 1:
The patent divides the semiconductor device into multiple separate chips (first semiconductor chip with SLC memory cell array and second semiconductor chip with MLC memory cell array) instead of integrating all functions into a single chip. This segmentation allows each chip to be optimized independently, maintaining high operating speed while preserving electrical properties and production yield through separate manufacturing processes.
2Speed
If the integration of semiconductor devices is increased to achieve high operating speed and low power consumption, then operating speed and power consumption are improved, but production yield deteriorates
Solution Approach 1:
By segmenting the device into multiple chips that can be manufactured separately using optimized processes for each memory type (SLC and MLC), the patent maintains high production yield while achieving high operating speed. Each chip can be produced independently at high yield rates without the compounding defects that would occur in a highly integrated single-chip design.
3Reliability
If multiple semiconductor chips are used to maintain electrical properties and production yield, then reliability and production yield are improved, but device complexity increases
Solution Approach 1:
The patent combines multiple semiconductor chips (first chip with SLC memory and second chip with MLC memory) into a single semiconductor package that functions as an integrated storage device. This merging approach maintains the electrical properties and production yield benefits of separate chips while presenting a unified interface to the external system, managing the complexity through standardized packaging and connection methods.
Data Source
AI summary
Disclosed are semiconductor packages and electronic systems. The semiconductor package comprises a first semiconductor chip that includes a first peripheral circuit structure and a first memory cell structure on the first peripheral circuit structure and a second semiconductor chip that includes a second peripheral circuit structure and a second memory cell structure on the second peripheral circuit structure. The first peripheral circuit structure includes a first substrate, a controller on the first substrate, and a first driver circuit on the first substrate. The second peripheral circuit structure includes a second substrate and a second driver circuit on the second substrate. The controller is electrically connected to the first driver circuit and the second driver circuit.