Memory IC Package Module for Stacked Chip Yield
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory IC chip packaging methods face challenges in increasing memory capacity while maintaining high production yield, as the number of stacked chips increases, leading to higher probabilities of bonding errors and limited flexibility in meeting customer-specific memory requirements.
Innovation Solution
A package module design featuring a ground pad, lower and upper contact pads, lead frames, and a molding layer, where the contact pads are exposed to facilitate easy stacking and soldering, allowing for expanded memory capacity with high production yield and flexibility in meeting customer requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked chips is increased to increase memory capacity, then the memory capacity is improved, but the production yield deteriorates due to higher probability of bonding errors
Solution Approach 1:
The package module is divided into separable components: a package body containing the memory IC chip, and a separate circuit board with contact pads. This segmentation allows independent manufacturing and testing of each component, reducing the cumulative bonding error probability while maintaining high memory capacity through multiple stacked chips.
Solution Approach 2:
Lead frames serve as intermediary elements between the memory IC chip and the circuit board. The lead frames facilitate electrical connection and mechanical support, enabling reliable bonding interfaces that reduce error propagation when stacking multiple chips to increase capacity.
2Quantity of substance
If the number of stacked chips is increased to increase memory capacity, then the memory capacity is improved, but the complexity of bonding procedures increases
Solution Approach 1:
The bonding process is segmented into two distinct stages: first bonding the memory IC chip to the package body, then bonding the assembled package module to the circuit board. This segmentation simplifies the overall procedure by allowing standardized interfaces at each stage, making it easier to manage complex multi-chip stacking for increased capacity.
Solution Approach 2:
The package body serves multiple functions: it provides mechanical support for the memory IC chip, electrical connection through integrated contact pads, and structural protection. This multi-functionality reduces the number of separate components and bonding steps needed when stacking multiple chips, thereby simplifying procedures while maintaining high memory capacity.
3Device complexity
If the memory IC chip set is packaged with fixed capacity, then the packaging structure is simplified, but the flexibility to meet customer-specific memory requirements deteriorates
Solution Approach 1:
The packaging system is designed with dynamic configurability: the circuit board can be configured with different numbers and arrangements of contact pads to match various memory capacity requirements. This allows the same basic package body design to be adapted for different customer needs by simply modifying the circuit board configuration, maintaining structural simplicity while achieving high versatility.
Solution Approach 2:
The separation between the fixed package body and the configurable circuit board enables flexibility. The package body remains a standardized, simple structure, while the circuit board can be customized for different memory capacities by adjusting the number of contact pads and their arrangement, thus meeting diverse customer requirements without complicating the core packaging design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enables efficient stacking of memory IC chip layers with high production yield and flexibility to meet varying customer memory capacity needs, reducing the risk of bonding errors and allowing for scalable memory expansion.
Implementation Method 1
a molding layer to package and enclose the ground pad, the plurality of lower contact pads, the at least a first memory IC chip, the plurality of lead frames and the plurality of upper contact pads, and curing the same
Implementation Method 2
each of the plurality of first solder pads is electrically connected to one of the plurality of lower contact pads via one of a plurality of golden lines
Implementation Method 3
Each of the plurality of lead frames is correspondingly soldered to one of the plurality of lower contact pads. Each of the plurality of upper contact pads is correspondingly soldered to one of the plurality of lead frames
Data Source
AI summary
The present invention relates to a package module for a memory IC chip, in which first solder pads provided on an upper surface of the memory IC chip is electrically connected to lower contact pads provided on the periphery of the ground pad, lower contact pads is soldered upward with lead frames and upper contact pads, and lastly a molding layer is used for packaging and enclosing the above elements, while only exposing the lower contact pads and the upper contact pads. Therefore, it will facilitate that each of upper contact pads of a lower layer is correspondingly soldered to one of lower contact pads of an upper layer as the upper layer and the lower layer are stacked together. Thus, it is capable of obtain high acceptable production yield, while accomplishing the object of expanding the memory capacity in total when stacking the layers of the package structure.