Memory Package Substrate Recess for Higher Chip Stack Density
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Solution Overview
Problem
The challenge of integrating multiple NAND flash memory chips in a solid-state drive (SSD) package is exacerbated by thermal management, power consumption, physical space constraints, signal integrity, manufacturing complexity, and reliability issues, particularly in compact designs where the stack height of memory chips is limited by the package dimensions.
Innovation Solution
The implementation of a substrate with a recess or cutout opening allows memory chips to partially sink below the substrate surface, enabling more chips to be stacked while maintaining wire access, achieved through the use of a conductive wire coupling and a temporary carrier like glass or molten structure for assembly, thereby increasing storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chips are stacked on top of a substrate, then storage capacity increases, but package height increases
Solution Approach 1:
The patent applies nesting by placing memory chips within a recess formed in the substrate, effectively nesting the chips inside the substrate volume rather than stacking them externally. This allows multiple chips to be integrated while maintaining a compact package height, as the chips occupy the internal recess space rather than adding to the external dimensions.
Solution Approach 2:
The patent transitions from vertical stacking (adding height in the Z-dimension) to horizontal integration within a recess (utilizing X-Y plane space). By forming a recess in the substrate and placing chips within it, the design moves the storage capacity increase from the vertical dimension to the horizontal plane, thereby increasing storage without proportionally increasing package height.
2Quantity of substance
If more memory chips are integrated, then storage capacity increases, but manufacturing complexity increases
Solution Approach 1:
The patent segments the substrate into different regions: a recess area for memory chip integration and a non-recess area for controller chip mounting. This segmentation allows different manufacturing processes to be applied to different regions - the recess area accommodates stacked memory chips while the non-recess area handles traditional planar controller integration, thereby managing manufacturing complexity through functional zoning.
Solution Approach 2:
The recess is formed in the substrate before the memory chips are mounted and wire-bonded. This preliminary action of creating the recess structure in advance simplifies the subsequent chip integration process, as the recess provides a pre-prepared receptacle that guides chip placement and reduces the complexity of aligning and securing multiple chips during assembly.
3Quantity of substance
If memory chips are stacked vertically, then storage capacity increases, but wire access becomes difficult
Solution Approach 1:
The patent uses wire bonding to connect only the necessary pads on the memory chips to the substrate, rather than attempting to access all potential connection points. The wire bonding process is applied selectively to establish the required electrical connections, achieving sufficient connectivity without the excessive complexity of comprehensive wiring, thereby maintaining ease of operation while supporting vertical chip stacking.
Solution Approach 2:
The substrate acts as an intermediary between the stacked memory chips and the external circuitry. The recess in the substrate provides a structured interface that facilitates wire access to the chips, as the substrate's top surface remains accessible for wire bonding while the chips are positioned within the recess. This intermediary structure mediates between the need for vertical integration and the requirement for electrical connectivity.
Data Source
AI summary
This application is directed to packaging technology for providing an electronic device (e.g., a memory device). A memory device includes a stack of memory chips, a device substrate, and a conductive wire. The stack of memory chips includes a first memory chip having a chip pad that is formed on a surface of the first memory chip. The device substrate includes a plurality of substrate pads formed on a front surface of the device substrate. The front surface has a front opening, and the device substrate receives the stack of memory chips via the front opening of the front surface. The conductive wire is coupled to the front surface and the stack of memory chips, and is configure to couple the chip pad and one of the substrate pads electrically. In some embodiments, the device substrate includes a cutout opening that goes through an entire thickness of the device substrate.