Hybrid-Bonded Memory Package with Mid-Array Word Line Driver
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components into a given area while maintaining performance, including increased complexity in routing connections between memory and circuitry devices, leading to higher latency, power consumption, and reduced device performance.
Innovation Solution
The solution involves bonding memory devices directly to circuitry devices using System on Integrated Chip (SoIC) technology, such as hybrid bonding, which simplifies routing, reduces contact resistance, and minimizes latency by forming metal-to-metal and dielectric-to-dielectric bonds, allowing for a more flexible and efficient connection between memory cells and functional circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory devices and circuitry devices are integrated with extensive routing connections, then functionality is achieved, but latency increases and performance decreases
Solution Approach 1:
The patent merges memory devices and circuitry devices into a single integrated package with direct bonding, eliminating separate routing paths. Memory cells are directly connected to functional circuits through bonded interconnect structures, reducing the number of routing stages and minimizing signal transmission latency while maintaining full device functionality.
Solution Approach 2:
The patent transitions from planar routing connections to three-dimensional vertical stacking with direct bonding. By bonding memory devices to circuitry devices in the vertical dimension, the patent creates shorter connection paths through the stack rather than routing signals across distant planar traces, thereby reducing latency and improving performance.
2Productivity
If feature size is reduced to increase integration density, then more components fit in given area, but routing complexity increases
Solution Approach 1:
The patent resolves routing complexity by moving from two-dimensional planar routing to three-dimensional vertical integration. Multiple memory devices and circuitry devices are stacked and bonded together, allowing connections to be made vertically through the stack rather than horizontally across crowded planes, thus maintaining high integration density while simplifying routing paths.
Solution Approach 2:
The patent segments the integrated device into distinct bonded layers (memory devices and circuitry devices) that can be independently optimized. Each layer contains specific functional elements, and routing is simplified by establishing direct vertical connections between corresponding elements in adjacent layers, reducing the overall routing complexity compared to monolithic integration.
3Adaptability or versatility
If functional circuits are included within memory device, then complete functionality is achieved, but connection length increases and power consumption rises
Solution Approach 1:
The patent combines memory devices and circuitry devices containing functional circuits into a single bonded package with direct interconnect structures. This merging places functional circuits immediately adjacent to memory cells through vertical bonding, minimizing connection length and reducing the energy required for signal transmission while maintaining complete read/write functionality.
Solution Approach 2:
The patent introduces bonded interconnect structures as intermediaries that directly couple memory devices to circuitry devices containing functional circuits. These interconnect structures serve as short, efficient transmission paths that eliminate long routing traces, thereby reducing power consumption while enabling complete memory functionality through the bonded interface.
Data Source
AI summary
Packaged memory devices including memory devices hybrid bonded to logic devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first memory die including a first memory cell electrically coupled to a first word line; a second memory cell electrically coupled to the first word line; and a first interconnect structure electrically coupled to the first word line; a circuitry die including a second interconnect structure, a first conductive feature of the first interconnect structure being bonded to a second conductive feature of the second interconnect structure through metal-to-metal bonds; and a word line driver electrically coupled to the first word line between the first memory cell and the second memory cell, the word line driver being electrically coupled to the first word line through the first interconnect structure and the second interconnect structure.