Distributed Memory Packet Sequencing Across Parallel Data Links
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Solution Overview
Problem
In a parallel and distributed computing system where multiple computers are interconnected via multiple data links, the arrival order of remote memory operation request packets is disturbed, leading to broken memory consistency due to load distribution across the links.
Innovation Solution
A parallel and distributed computing system that includes transmission and reception number-counting units to ensure the arrival order of operation request packets by attaching count numbers to the packets, allowing processing only when count numbers are consecutive, and updating these counts as necessary to maintain memory consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple data links are used to interconnect computers in a parallel and distributed computing system, then communication performance and bandwidth are improved, but packet arrival order is disturbed and memory consistency is broken
Solution Approach 1:
The transmission-side process attaches a count number to each operation request packet before transmission. This preliminary action allows the reception-side process to verify packet arrival order without requiring complex synchronization mechanisms, thus maintaining memory consistency while utilizing multiple data links for improved communication performance
Solution Approach 2:
The reception-side process uses the count number attached to packets to feedback whether the arrival order is correct. By comparing the count number with expected sequence, the system can detect and handle out-of-order packets, ensuring memory consistency is maintained despite using multiple parallel data links
2Productivity
If operation request packets are distributed to multiple data links, then processing throughput is improved, but packet arrival order disturbance increases
Solution Approach 1:
By attaching count numbers to packets before transmission, the system enables efficient packet distribution across multiple links while maintaining order information. This allows high processing throughput through parallel link utilization while preventing arrival order disturbances through the count number verification mechanism
3Reliability
If count number verification is performed for each packet, then memory consistency is maintained, but processing overhead increases
Solution Approach 1:
The system changes the verification parameter from complex synchronization protocols to simple count number comparison. This parameter change maintains memory consistency with minimal processing overhead, as the count number is a single integer that can be quickly compared without requiring complex state management or additional communication
Data Source
AI summary
The present invention is to solve the breaking of memory consistency caused by disturbance of packet arrival order in an environment in which a plurality of computers are interconnected via a plurality of data links and the plurality of computers perform communication synchronization by MBCF with each other. A transmission-side process includes a transmission number-counting unit that counts the number of transmission of the operation request packet for each reception-side process and attaches a count number before or after counting-up of the operation request packet to the operation request packet, a reception-side process includes a reception number-counting unit that counts the number of reception of the operation request packet for each transmission-side process, and a transmission destination computer performs processing of the operation request packet when a count number of the reception number-counting unit and the count number attached to the operation request packet are consecutive.