Memory Packet Strobing for Data Transmission Overhead Reduction
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Solution Overview
Problem
Conventional serial bus designs for memory systems incur significant overhead due to codes used to identify commands and parameters, impacting performance and space efficiency in data transmission.
Innovation Solution
The implementation of a memory system using packet strobing, where command and data packets are delineated by strobe signals, reducing the need for explicit codes and enhancing data transmission efficiency by allowing simultaneous input and output of packets with strobe signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional serial bus designs use codes to identify commands and parameters, then data transmission can be achieved, but overhead increases and performance deteriorates
Solution Approach 1:
The patent extracts and removes the overhead codes from the data transmission protocol. Instead of using coded identifiers for commands and parameters, the invention uses a streamlined packet structure where the strobe signal itself delineates packet boundaries and types, eliminating the need for explicit identification codes and reducing overhead.
Solution Approach 2:
The invention changes the fundamental parameter of data identification from coded values to temporal signaling. By using the strobe signal's presence and timing to identify packet types and boundaries rather than relying on coded identifiers within the data stream, the system achieves higher efficiency while maintaining reliability.
2Productivity
If packet strobing is implemented to reduce overhead, then data transmission efficiency improves, but signal complexity increases
Solution Approach 1:
The patent merges the functions of data signaling and control signaling into a unified packet strobe interface. The same data lines carry both data and control information, while a single strobe signal performs multiple functions including packet delineation, synchronization, and command identification, thereby reducing overall system complexity despite improved efficiency.
3Speed
If parallel bus is used to transfer data and control signals, then transmission speed is high, but wire count and layout complexity increase
Solution Approach 1:
The invention transitions from a spatial parallel bus architecture to a temporal serial packet architecture. Instead of using multiple wires simultaneously (spatial dimension), the system uses time-division multiplexing on fewer wires (temporal dimension), achieving comparable effective bandwidth with reduced physical complexity and improved scalability.
Data Source
AI summary
In an embodiment, a memory device comprises memory, a first data link, a first input, a second input, a second data link, a first output and a second output. The first data link is configured to input one or more packets into the memory device. The first input is configured to input command strobe signals into the memory device that delineate command packets that are input into the memory device via the first data link. The second input is configured to input data strobe signals into the memory device that delineate data packets that are input into the memory device via the first data link. The first and second outputs are configured to output the command strobe signal and data strobe signal, respectively. The second data link is configured to output packets from the memory device.