Memory Pad Alignment for Interconnection Simplification
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Solution Overview
Problem
The complexity of interconnection patterns in memory systems, particularly where page buffers and bit line selection units are connected, leads to increased area usage due to the presence of global and bit line pads, complicating the layout of connection metal lines.
Innovation Solution
Aligning global pads in the page buffer area with bit line pads in the bit line selection area simplifies the connection metal line patterns and allows for adjustable bit line selection unit sizes, thereby minimizing the overall memory area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If connection metal lines are routed to connect page buffers and bit line selection units while avoiding global pads and bit line pads, then the connection is achieved, but the interconnection pattern becomes complicated
Solution Approach 1:
The global pads and bit line pads are pre-aligned in specific positions before metal line routing is performed. This preliminary alignment of pads ensures that subsequent metal line connections follow simple, regular patterns rather than complex avoidance routes, directly resolving the contradiction between achieving connections and maintaining pattern simplicity
2Area of stationary object
If page buffer area and bit line selection area are arranged adjacent to each other, then area efficiency is improved, but metal line pattern complexity increases
Solution Approach 1:
Pads in the adjacent page buffer area and bit line selection area are pre-aligned in corresponding positions before metal line routing. This preliminary alignment enables simple horizontal or vertical metal line connections between adjacent areas, maintaining pattern simplicity while achieving area efficiency through adjacent arrangement
3Area of stationary object
If bit line selection unit size is fixed, then manufacturing is simplified, but area optimization is limited
Solution Approach 1:
The bit line selection unit is designed with adjustable size capability, allowing the unit dimensions to be dynamically optimized based on specific memory layout requirements. This dynamic sizing enables area optimization without fundamentally complicating the manufacturing process, as the unit structure remains consistent while dimensions can be adapted
Data Source
AI summary
A memory in accordance with an embodiment of the present invention may include a first page buffer, a second page buffer arranged adjacent to the first page buffer in a first direction, a global pad arranged between the first page buffer and the second page buffer, and a first bit line selection unit arranged adjacent to the first page buffer and the second page buffer in a second direction substantially perpendicular to the first direction, wherein a first bit line pad is formed at a center of the a first bit line selection unit.