Semiconductor Memory Pad Distribution for Bonding Alignment
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Solution Overview
Problem
The existing semiconductor memory devices face challenges in increasing the pitch of pads without expanding the device size, which affects the alignment margin and yield during the wafer bonding process, leading to potential bonding defects.
Innovation Solution
The semiconductor memory device incorporates a design where the pads are distributed in high voltage regions with alternating low voltage regions, allowing for increased pitch without increasing the device size, and the pads are configured differently from the bit line select transistors to enhance alignment margins and reduce defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the pitch of pads is increased to improve alignment margin, then the device size must be increased, but increasing device size is not desirable
Solution Approach 1:
The pads are arranged in an alternating pattern between high voltage regions and low voltage regions, utilizing the spatial dimension of voltage region distribution. This allows pads to be positioned in multiple discrete locations along the bit line direction, effectively increasing pitch without requiring overall device expansion.
Solution Approach 2:
Different regions of the device are assigned different voltage characteristics (high voltage regions alternating with low voltage regions). The pads are strategically placed in high voltage regions, creating local quality variations that enable increased pitch while maintaining functional requirements in specific areas.
2Area of stationary object
If pads are densely arranged to reduce device size, then alignment margin during bonding decreases, but reducing alignment margin increases bonding defects
Solution Approach 1:
The continuous pad arrangement is segmented into discrete pad groups located in alternating high voltage and low voltage regions. This segmentation creates natural spacing between pad groups, increasing the effective pitch and alignment margin without requiring overall device size increase.
Solution Approach 2:
The pad distribution utilizes the voltage region dimension as an organizing principle, arranging pads in alternating high and low voltage regions along the bit line direction. This dimensional organization automatically provides spacing and alignment margins while maintaining compact device footprint.
3Reliability
If pads are placed close together to minimize device area, then bonding defects increase due to reduced alignment margin, but increasing pitch increases device area
Solution Approach 1:
High voltage regions are designated as local zones for pad placement, alternating with low voltage regions. This local quality assignment ensures pads are positioned in optimal locations with sufficient spacing, improving bonding reliability without requiring uniform expansion of the entire device area.
Solution Approach 2:
The pad layout is segmented into discrete groups within high voltage regions, separated by low voltage regions. This segmentation naturally creates alignment margins and reduces bonding defects while maintaining compact overall device area through efficient spatial utilization.
Data Source
AI summary
A semiconductor memory device includes: a plurality of page buffers disposed on a substrate; and a plurality of pads exposed to one surface of a dielectric layer covering the page buffers, and coupled to the respective page buffers. The substrate comprises a plurality of high voltage regions and a plurality of low voltage regions which are alternately disposed in a second direction crossing a first direction. Each of the plurality of page buffers comprises a sensing unit and a bit line select transistor coupled between the sensing unit and the one of the plurality of pads. The bit line select transistors of the plurality of page buffers are disposed in the plurality of high voltage regions, and the plurality of pads are distributed and disposed in a plurality of pad regions which correspond to the high voltage regions and are spaced apart from each other in the second direction.