3D Memory Cell Bonding Pad Layout for Dummy Pattern Protection
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity while maintaining reliability and efficiency, particularly in three-dimensionally arranged memory cells.
Innovation Solution
A semiconductor device design incorporating a peripheral circuit structure on a semiconductor substrate with three-dimensionally arranged memory cells, featuring a stacked structure with insulating layers and electrodes, and a dummy pattern at the same level as the semiconductor layer, along with a photosensitive insulating layer that varies in thickness to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the thickness of the photosensitive insulating layer is reduced to improve etching efficiency and productivity, then the etching process becomes faster and more efficient, but the dummy pattern becomes vulnerable to etching damage and reliability deteriorates
Solution Approach 1:
The photosensitive insulating layer is designed with non-uniform thickness: a first thickness in the first region (overlapping the external connection pad) and a second thickness in the second region (overlapping the dummy pattern). This local variation allows the layer to provide enhanced protection where needed (over the dummy pattern) while maintaining overall process efficiency.
Solution Approach 2:
The photosensitive insulating layer is formed as a preliminary protective structure before the etching process. By pre-establishing this layer with appropriate thickness distribution, the dummy pattern is protected from etching damage before the harmful etching action occurs, resolving the contradiction between etching efficiency and pattern integrity.
2Quantity of substance
If three-dimensionally arranged memory cells are implemented to increase data storage capacity, then storage density improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The memory cells are arranged in a three-dimensional stacked structure with multiple layers extending in the vertical direction. This transitions from traditional two-dimensional planar arrangements to three-dimensional vertical stacking, thereby increasing storage capacity while managing device complexity through systematic layering and the use of dummy patterns for process control.
3Reliability
If the photosensitive insulating layer thickness is made non-uniform to protect dummy patterns, then reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The thickness parameter of the photosensitive insulating layer is deliberately varied across different regions of the device. By changing this physical parameter spatially (first thickness in first region, second thickness in second region), the layer provides differentiated protection levels that enhance reliability while the variation is achieved through controlled manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances the reliability and efficiency of data storage by preventing etching damage to dummy patterns, thereby improving the overall performance and longevity of the semiconductor device.
Implementation Method 1
a photosensitive insulating layer on the semiconductor layer and the dummy pattern
Data Source
AI summary
A semiconductor device includes a peripheral circuit structure including peripheral circuits on a substrate and first bonding pads electrically connected to the peripheral circuits and a cell array structure including memory cells on a semiconductor layer and second bonding pads electrically connected to the memory cells and bonded to the first bonding pads. The cell array structure includes a stacked structure including insulating layers and electrodes, an external connection pad on a surface of the semiconductor layer, a dummy pattern at a same level as the semiconductor layer relative to the substrate, and a photosensitive insulating layer on the semiconductor layer and the dummy pattern. A first thickness of a portion of the photosensitive insulating layer vertically overlapping the external connection pad is greater than a second thickness of another portion of the photosensitive insulating layer vertically overlapping the dummy pattern.