Memory Structure Pad Layers for Contact Reliability
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Solution Overview
Problem
The miniaturization of semiconductor structures leads to challenges such as increased contact resistance due to smaller landing areas for connectors, causing contact difficulties and mismatches, which existing technologies have not adequately addressed.
Innovation Solution
A memory structure comprising alternately stacked conductive and insulating strips on a substrate with additional pad layers formed above the channel layers, enhancing connectivity and conductivity, and a method involving the formation of sacrificial material replacement with pad material to create these layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If elements and spaces in a semiconductor device are continuously shrunk to decrease volume and weight, then portability is improved, but contact difficulty and mismatch increase leading to higher relative resistances
Solution Approach 1:
The patent introduces pad layers with larger lateral dimensions in the planar direction while maintaining vertical integration. This dimensional transition from uniform scaling to selective lateral expansion in the pad region resolves the contradiction by providing larger contact areas without increasing overall device volume, thus improving contact reliability while maintaining portability.
Solution Approach 2:
The pad layers are designed with locally enhanced properties (larger area, different material composition) specifically at the connector contact regions, while other parts of the device continue to scale down. This localized quality enhancement addresses contact reliability issues without compromising the overall miniaturization benefits for portability.
2Area of moving object
If landing areas for connectors are reduced to enable miniaturization, then device size decreases, but contact difficulty and mismatch increase
Solution Approach 1:
The pad layers extend laterally beyond the channel layers, creating enlarged landing areas in the planar dimension. This dimensional approach allows larger connector contact areas without increasing the vertical profile or overall device footprint, thereby improving ease of connector contact while maintaining miniaturization.
Solution Approach 2:
The pad layers are formed in advance before final connector assembly, providing pre-prepared contact surfaces with optimized geometry and material properties. This preliminary preparation of contact areas facilitates easier and more reliable connector mating operations.
Data Source
AI summary
A memory structure includes a substrate, a plurality of stacks, a plurality of memory layers, a plurality of channel layers and a plurality of pad layers. The stacks are disposed on the substrate. The stacks are separated from each other by a plurality of first trenches. The stacks include alternately arranged first stacks and second stacks. Each of the stacks includes alternately stacked conductive strips and insulating strips. The memory layers are partially disposed in the first trenches. The memory layers extend onto the stacks in a conformal manner. The channel layers are disposed on the memory layers in a conformal manner. The pad layers are at least disposed on the channel layers at positions substantially above the first stacks.