Semiconductor Memory Pad Layout for Narrower Contact Regions

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Solution Overview

Problem

Current semiconductor memory devices face challenges in optimizing the layout and manufacturing method of interconnect pads, leading to increased chip size and manufacturing costs due to wider contact pad regions and complex exposure processes.

Innovation Solution

The semiconductor memory device employs a two-stage or four-stage pad region layout with specific pad portion arrangements and a manufacturing method involving multiple resist patterns and sidewall processes to form conductive layers, reducing the X-direction width of contact pads and simplifying exposure requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional pad region layout is used, then contact pad width is sufficient for manufacturing, but chip area increases and manufacturing cost increases

Engineering Contradiction:
Improvecontact pad widthVSAvoidchip area
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The pad region is divided into multiple stages (first stage and second stage) along the Y-direction, allowing the contact pad to be formed through sequential patterning steps. This dimensional segmentation enables reduction of the X-direction width while maintaining manufacturing precision through the multi-stage exposure process

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The exposure process is segmented into multiple stages with different resist patterns. The first resist pattern forms the initial pad structure, and the second resist pattern refines the final contact pad dimensions. This segmentation allows precise control of contact pad width independent of the overall pad region area

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If conventional exposure process is used, then manufacturing process is simple, but exposure requirements become complex

Engineering Contradiction:
Improveexposure process simplicityVSAvoidexposure process complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The exposure process is divided into distinct stages, each with its own resist pattern requirements. The first stage uses a first resist pattern for initial pad formation, and the second stage uses a second resist pattern for final contact pad definition. This segmentation simplifies each individual exposure step while achieving the complex overall pattern through systematic multi-stage processing

Inventive Principle:
Principle #1Segmentation

3Manufacturing precision

If wider contact pad region is used, then manufacturing precision is improved, but chip area increases

Engineering Contradiction:
Improvecontact pad formation precisionVSAvoidpad region area
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The pad region is extended in the Y-direction through multi-stage patterning rather than increasing the X-direction width. The first and second resist patterns are applied sequentially along the Y-axis, enabling precise contact pad formation in the X-direction while containing the overall pad region area through controlled Y-direction extension

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12154648B2Semiconductor device, semiconductor memory device, and manufacturing method of semiconductor device
Publication Date: 2024.11.26 KIOXIA CORP
  • US12154648B2 patent drawing
  • US12154648B2 patent drawing
  • US12154648B2 patent drawing

AI summary

A semiconductor device according to one embodiment includes first and second conductors, a first insulator, and first and second contacts. The first conductor includes a first pad portion. The first pad portion includes first and second sub portions. Each of the first and second sub portions includes one and another end portions. The first sub portion is adjacent to the second pad portion. The second sub portion is adjacent to the first insulator. A length of the second sub portion of the first pad portion is less than a length of the first sub portion of the first pad portion.