3D Memory I/O Pad Over Mold Opening for Lower Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing data storage capacity and maintaining a high degree of integration, particularly in three-dimensional memory cell arrangements, which can lead to structural damage during bonding processes and increased parasitic capacitance.
Innovation Solution
A semiconductor memory device design featuring a cell substrate with stacked mold structures and channel structures, including a mold opening that exposes a portion of the second mold stack, allowing the input/output pad to overlap the mold opening, thereby protecting adjacent structures and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but structural integrity is compromised during bonding processes
Solution Approach 1:
The device is divided into a cell substrate and a separate pad structure. The mold opening segments the mold stack to expose the pad region, allowing the pad to be structurally separated from the three-dimensional memory cell array. This segmentation enables the pad to be reinforced independently while the memory cells maintain their high-density three-dimensional arrangement, resolving the contradiction between increased storage capacity and structural integrity during bonding.
2Device complexity
If input/output pad is positioned over cell array to improve degree of integration, then device integration is improved, but parasitic capacitance increases
Solution Approach 1:
The pad structure is extracted from the conventional planar configuration and repositioned vertically over the mold opening. By taking the pad out of the traditional cell array plane and positioning it above the exposed mold region, the design achieves high degree of integration through vertical stacking while simultaneously reducing parasitic capacitance by increasing the physical distance between the pad and the underlying memory cell structures.
Solution Approach 2:
The pad structure transitions from a two-dimensional planar arrangement to a three-dimensional vertical configuration above the mold opening. This dimensional change allows the pad to overlap the mold opening in the vertical direction, achieving better integration without increasing lateral parasitic capacitance, as the electric field lines are directed vertically rather than laterally through the cell array.
Data Source
AI summary
A semiconductor memory device includes a cell substrate including a first surface and a second surface opposite to the first surface, a first mold stack including a plurality of first gate electrodes sequentially stacked on the first surface, a second mold stack including a plurality of second gate electrodes sequentially stacked on the first mold stack, a first channel structure extending in a first direction with respect to the first surface and crossing the plurality of first gate electrodes and the plurality of second gate electrodes, and an input/output pad on the second surface, wherein the first mold stack includes a mold opening that exposes a portion of the second mold stack, and at least a portion of the input/output pad overlaps the mold opening in the first direction.