Semiconductor Memory Pad Multiplexing for Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices require a large number of pads for testing and signal input/output, which increases chip size and complicates testing, making it difficult to efficiently test multiple devices simultaneously.
Innovation Solution
A semiconductor memory device design that includes a pad for external signal reception, a reference voltage pad, an internal reference voltage generator, a reference voltage supply unit, and a signal selector, allowing for the selection between external and internal reference voltages to control signal input/output through a reduced number of pads, enabling testing without increasing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of pads is increased to support more signal input/output and testing functions, then the device functionality and testing capability are improved, but the chip size increases
Solution Approach 1:
The reference voltage pad is designed to serve multiple functions: it can receive external reference voltage during normal operation, and can also be used to input/output internal signals during wafer test. This multi-functionality allows the same pad to support both device functionality and testing requirements, thereby increasing adaptability without increasing the number of pads or chip size.
2Adaptability or versatility
If the number of pads is increased to support more signal input/output and testing functions, then the device functionality and testing capability are improved, but the testing complexity increases
Solution Approach 1:
The reference voltage pad serves dual purposes: normal operation mode for receiving external reference voltage, and wafer test mode for inputting/outputting internal signals. This eliminates the need for separate dedicated test pads, thereby improving testing capability while reducing testing complexity by using existing pads for testing functions.
3Area of stationary object
If the number of pads is reduced to decrease chip size, then the chip size decreases, but the testing efficiency decreases
Solution Approach 1:
The reference voltage pad is configured to perform both its traditional reference voltage reception function during normal operation and internal signal input/output function during wafer test. This multi-functionality enables efficient testing of multiple chips simultaneously using fewer pads, thereby reducing chip size while maintaining or improving testing efficiency.
Data Source
AI summary
A semiconductor memory device includes a pad for receiving an external signal through a first external pin, a reference voltage pad for receiving an external reference voltage through a second external pin, an internal reference voltage generator configured to generate an internal reference voltage using an external voltage in response to a reference voltage select signal, a reference voltage supply unit for generating the reference voltage select signal in response to a plurality of select signals, and selecting one reference voltage between the external reference voltage and the internal reference voltage to output the selected one as a reference voltage, a buffer for converting an output signal of the pad into an internal voltage level on the basis of the reference voltage, and a signal selector for controlling an internal signal to be inputted/outputted through the reference voltage pad in response to the plurality of select signals.