3D Memory Pad Overlap Layout for Low-Capacitance Bonding
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing data storage capacity and maintaining a high degree of integration, particularly in three-dimensional memory cell arrangements that are prone to structural damage and parasitic capacitance issues during bonding processes.
Innovation Solution
A semiconductor memory device design featuring a cell substrate with stacked mold structures and channel structures, including a mold opening that exposes a portion of the second mold stack, allowing the input/output pad to overlap the mold opening, thereby protecting adjacent structures and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but structural integrity deteriorates due to bonding process damage
Solution Approach 1:
The device is divided into a cell substrate and a separate pad structure. The mold opening segments the mold stack to expose the pad region, allowing the input/output pad to be positioned without compromising the three-dimensional memory cell structures. This segmentation enables independent optimization of storage density and bonding reliability.
Solution Approach 2:
The mold opening acts as an intermediary structure that mediates between the three-dimensional memory cell array and the input/output pad. By creating an exposed region through the mold stack, it provides a dedicated interface area for bonding operations without interfering with the integrity of the vertical channel and gate electrode structures.
2Reliability
If input/output pad is positioned to overlap mold structures for protection, then structural protection is improved, but parasitic capacitance increases
Solution Approach 1:
The mold opening extracts or removes the mold material from the pad region, creating an exposed area where the input/output pad can be positioned. This extraction eliminates the parasitic capacitance that would otherwise exist between the pad and the overlying mold structures, while still allowing the pad to benefit from the protective positioning within the overall device structure.
3Object-generated harmful factors
If mold opening is created to expose second mold stack for pad positioning, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The formation of the mold opening is merged with the existing mold stack fabrication process. The mold opening is created as part of the sequential stacking of mold structures, utilizing the same patterning and deposition techniques already employed for creating the multi-layer mold stack. This integration minimizes additional manufacturing steps while achieving the parasitic capacitance reduction.
Data Source
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AI summary
A semiconductor memory device includes a cell substrate (100) including a first surface (100a) and a second surface (100b) opposite to the first surface, a first mold stack, MS1, including a plurality of first gate electrodes, GSL, WL11-WL1n, sequentially stacked on the first surface (100a), a second mold stack, MS2, including a plurality of second gate electrodes, WL21-WL2n, SSL, sequentially stacked on the first mold stack, MS1, a first channel structure, CH1, extending in a first direction with respect to the first surface (100a) and crossing the plurality of first gate electrodes, GSL, WL11-WL1n, and the plurality of second gate electrodes, WL21-WL2n, SSL, and an input/output pad (380) on the second surface (100b), wherein the first mold stack, MS1, includes a mold opening, MSo, that exposes a portion of the second mold stack, MS2, and at least a portion of the input/output pad (380) overlaps the mold opening in the first direction.