3D Memory Pad Support Structure for Bonding Damage Reduction
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing data storage capacity while maintaining a high degree of integration and avoiding structural damage during bonding processes.
Innovation Solution
The semiconductor memory device incorporates a cell substrate with a channel structure extending vertically and intersecting gate electrodes, along with a landing pattern and support contact to form a load distribution structure, which enhances integration and protects underlying structures during bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are three-dimensionally arranged to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent implements three-dimensional stacking of memory cells by forming channel structures that extend in the vertical direction (first direction) and gate electrodes stacked in the second direction perpendicular to the channel structures. This vertical stacking approach increases storage capacity by utilizing the third dimension while maintaining a compact footprint on the substrate.
Solution Approach 2:
The memory device is divided into multiple stacked layers including cell substrates, landing patterns, and interlayer insulating films. Each layer performs a specific function, allowing for modular fabrication and assembly. The channel structures are segmented into multiple stacks along the vertical direction, with each stack containing multiple memory cells that can be independently controlled by gate electrodes.
2Productivity
If bonding process is performed to increase integration, then degree of integration is improved, but structural damage risk increases
Solution Approach 1:
The patent forms a landing pattern on the cell substrate before the bonding process. This landing pattern serves as a cushioning structure that absorbs mechanical stress and prevents direct transmission of bonding forces to the fragile channel structures and gate electrodes, thereby protecting them from damage during the bonding operation.
Solution Approach 2:
The landing pattern acts as an intermediary element between the cell substrate and the bonding interface. It provides a robust bonding surface that mediates the mechanical stresses during bonding, preventing these stresses from reaching the sensitive three-dimensional memory cell structures underneath.
3Area of stationary object
If input/output pad overlaps gate electrodes to reduce area, then area is reduced, but parasitic capacitance increases
Solution Approach 1:
The patent employs different insulating materials in different regions: a first interlayer insulating film with lower dielectric constant is formed in regions where input/output pads overlap with gate electrodes, while a second interlayer insulating film with higher dielectric constant is used in other regions. This local differentiation reduces parasitic capacitance in critical areas while maintaining overall device performance.
Data Source
AI summary
A semiconductor memory device may include a cell substrate including a first surface and a second surface opposite to the first surface, and a landing pattern including a third surface and a fourth surface opposite to the third surface, with the landing pattern spaced apart from the cell substrate in a horizontal direction. The semiconductor memory device may include a plurality of gate electrodes sequentially stacked on the first surface and the third surface, a channel structure on the cell substrate, the channel structure extending vertically and intersecting the plurality of gate electrodes, an upper insulating film covering the second surface and the fourth surface, an input/output pad on the upper insulating film, the input/output pad overlapping at least a portion of the plurality of gate electrodes in the vertical direction, and a support contact extending through the upper insulating film and connecting the landing pattern and the input/output pad.