3D Memory I/O Pad Structure With Support Contact for Bonding Reliability
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in increasing data storage capacity while maintaining a high degree of integration and avoiding structural damage during bonding processes.
Innovation Solution
The semiconductor memory device features a cell substrate with a channel structure extending vertically and intersecting gate electrodes, an input/output pad overlapping the gate electrodes, and a support contact connecting the landing pattern to the input/output pad, enhancing integration and structural support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are three-dimensionally arranged to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent implements three-dimensional memory cell arrangement by stacking multiple gate electrodes (first gate electrode, second gate electrode, third gate electrode) vertically on the channel structure. This vertical stacking approach transitions from two-dimensional to three-dimensional memory organization, significantly increasing storage capacity while maintaining a compact footprint by utilizing the vertical dimension for additional storage layers.
Solution Approach 2:
The memory device is segmented into distinct functional regions: cell substrate containing memory cells, landing pattern for electrical connection, and peripheral circuit structure for control logic. This segmentation allows independent optimization of each region and simplifies the overall device architecture by separating storage functions from control functions, thereby managing device complexity systematically.
2Device complexity
If input/output pad overlaps gate electrodes to improve integration, then degree of integration is improved, but risk of structural damage during bonding increases
Solution Approach 1:
The patent introduces an upper insulating film as an intermediary layer between the input/output pad and the underlying gate electrodes. This insulating film serves as a protective mediator that prevents direct mechanical contact and potential damage during bonding processes, while still allowing the input/output pad to overlap the gate electrodes for improved integration and reduced parasitic capacitance.
Solution Approach 2:
The upper insulating film is formed in advance before the bonding process, providing beforehand cushioning and protection to the delicate gate electrode structures. This preventive measure ensures that the gate electrodes are shielded from mechanical stress and damage that could occur during subsequent bonding operations, thereby maintaining structural integrity while enabling high integration.
3Reliability
If support contact connects landing pattern to input/output pad to reduce parasitic capacitance, then performance is improved, but manufacturing complexity increases
Solution Approach 1:
The support contact structure merges multiple functions into a single integrated component: it provides electrical connection between the landing pattern and input/output pad, serves as a mechanical support structure, and simultaneously acts as a parasitic capacitance reduction element. This merging of functions reduces the number of separate components needed and simplifies the overall manufacturing process while achieving multiple performance goals.
Data Source
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AI summary
A semiconductor memory device may include a cell substrate including a first surface and a second surface opposite to the first surface, and a landing pattern including a third surface and a fourth surface opposite to the third surface, with the landing pattern spaced apart from the cell substrate in a horizontal direction. The semiconductor memory device may include a plurality of gate electrodes sequentially stacked on the first surface and the third surface, a channel structure on the cell substrate, the channel structure extending vertically and intersecting the plurality of gate electrodes, an upper insulating film covering the second surface and the fourth surface, an input/output pad on the upper insulating film, the input/output pad overlapping at least a portion of the plurality of gate electrodes in the vertical direction, and a support contact extending through the upper insulating film and connecting the landing pattern and the input/output pad.